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Advantages of J-Link versus other probes

Q: What is the advantage of J-Link versus simple probes such as FTDI based systems?
A: J-Link has numerous advantages. One of the biggest advantages is the J-Link software supplied by SEGGER, which allows using it with common IDEs, the availability of unlimited flash breakpoints for people debugging software which runs in the flash of  microcontrollers, as well as the high speed of the J-Link and the simple and very fast download into flash memory.

In contrast to most of the simple probes, it supports adaptive clocking as well as SWD and SWO. It also works more stable since it is not just a dump USB to JTAG converter, but uses the intelligence of the built-in CPU, providing a more robust communication, especially in situations where the target CPU runs at low clock speeds.

Using J-Link in my application

Q: I want to write my own application and use J-Link. Is this possible?
A: Yes. We offer a dedicated Software Developer Kit (SDK). It allows using the full J-Link functionality. [More info...]

J-Link Script files

Q: The core of my target system could not be recognized automatically. Is there a way to configure my device in order to communicate with J-Link?
A: Yes! In most cases the J-Link auto-detection works fine and recognizes the core of a device automatically. However, in some cases the auto-detection of J-Link does not work e.g. if the core is not present in the JTAG chain by default and needs to be enabled by sending a command to another device in the JTAG-chain. In such cases, the connection sequence of J-Link can be customized by using a J-Link script file which is executed before the communication between J-Link and the target system starts. The script file allows maximum flexibility, so almost any target initialization which is necessary, can be supported.

Adaptive clocking

Q: What is adaptive clocking and when and why would I use it?
A: If the target provides the RTCK signal, select the adaptive clocking function to synchronize the JTAG clock (TCK) to the processor clock outside the core. This ensures there are no synchronization problems over the JTAG interface. If you use the adaptive clocking feature, transmission delays, gate delays, and synchronization requirements result in a lower maximum clock frequency than with nonadaptive clocking. This is the recommended JTAG speed used to connect to ARM7/9 -S cores.

Multi-core debugging

Q: I have multiple ARM cores in my JTAG chain. How can I debug them (simultaneously) with J-Link?
A: Simple: Two or more debuggers can use the same J-Link simultaneously. Multi-core debugging requires multiple debuggers or multiple instances of the same debugger. You need to tell your debugger which device in the scan chain you want to debug. Additional special settings are not required.

Using multiple J-Links

Q: May I work with more than one J-Link at one time on the same machine?
A: Yes, you can connect an unlimited number of J-Links to your PC. No special configuration is required, since each J-Link is registered with its unique serial number at the PC, allowing it to have multiple J-Links connected in parallel.

Supported CPUs

Q: Which CPUs are supported by J-Link?
A: J-Link works with ARM7/9/11, Cortex-A5/A8/A9, Cortex-M0/M0+/M1/M3/M4/M7, Cortex-R4/R5, Microchip PIC32 and Renesas RX100/RX200/RX600 series CPUs.

Maximum JTAG speed

Q: What is the maximum JTAG speed supported by J-Link?
A: The maximum JTAG speed supported by J-Link BASE is 15MHz. J-Link ULTRA+ supports a maximum JTAG speed of 50MHz.

Maximum download speed

Q: What is the maximum download speed into RAM?
A: The maximum download speed is currently about 1 MByte/sec for J-Link and 3 MBytes/sec for J-Link ULTRA+ and J-Link PRO when downloading into RAM. However, the actual speed depends on various factors, such as JTAG, clock speed, host CPU core etc.

Read status of JTAG pins

Q: Can J-Link read back the status of the JTAG pins?
A: Yes, the status of all pins can be read. This includes the outputs of J-Link as well as the supply voltage, which can be useful to detect hardware problems on the target system.

J-Link support of ETB

Q: Does J-Link support the Embedded Trace Buffer (ETB)?
A: Yes. J-Link supports ETB. Most current ARM7 / ARM9 chips do not have ETB built-in.

J-Link support of ETM

Q: Does J-Link support the Embedded Trace Macrocell (ETM)?
A: No. ETM requires another connection to the ARM chip and a CPU with built-in ETM. Most current ARM7 / ARM9 chips do not have ETM built-in.