JTAG/SWD Debug Probe with USB Interface
The BASE version of the market-leading debug probe family. Top models of the J-Link family are J-Link PRO, PLUS and ULTRA+.
J-Link BASE
J-Link BASE is a USB powered JTAG debug probe supporting a large number of CPU cores. Based on a 32-bit RISC CPU, it can communicate at high speed with the supported target CPUs. J-Link is used around the world in tens of thousand places for development and production (flash programming) purposes.
J-Link BASE is available in two form factors with identical function: J-Link BASE Classic and J-Link BASE Compact.
The J-Link debug probes are supported by all major IDEs including Eclipse, GDB-based IDEs and SEGGER Embedded Studio. For a complete list, please refer to Supported IDEs.
Including all models, more than 500,000 J-Links have been shipped so far, making J-Link probably the most popular debug probe for ARM cores and the de-facto standard.
Specifications
| Specification | Value |
|---|---|
| Supported OS | Microsoft Windows (x86/x64), Linux (x86/x64/Arm), macOS (x86) |
| Electromagnetic compatibility (EMC) | EN 55022, EN 55024 |
| Operating temperature | +5°C ... +60°C |
| Storage temperature | -20°C ... +65 °C |
| Relative humidity (non-condensing) | Max. 90% rH |
| Mechanical | |
| Size of J-Link BASE Classic (without cables) | 100mm x 53mm x 27mm |
| Weight of J-Link BASE Classic (without cables) | 70g |
| Size of J-Link BASE Compact (without cables) | 47mm x 40mm x 14mm |
| Weight of J-Link BASE Compact (without cables) | 20g |
| Available Interfaces | |
| USB interface (J-Link BASE) | USB 2.0 (Hi-Speed); USB Type B |
| USB interface (J-Link BASE Compact) | USB 2.0 (Hi-Speed); Micro USB |
| Target interface | JTAG/SWD 20-pin |
| JTAG/SWD Interface, Electrical | |
| Power supply | USB powered Max. 50mA + Target Supply current. |
| Target interface voltage (VIF) | 1.2V ... 5V |
| Current drawn from target voltage sense pin (VTRef) | < 25µA |
| Target supply voltage | 5V (derived from USB voltage) |
| Target supply current | Max. 300mA |
| Reset type | Open drain. Can be pulled low or tristated |
| Reset low level output voltage | VOL <= 10% of VIF |
| For the whole target voltage range (1.2V <= VIF <= 5V) | |
| LOW level input voltage (VIL) | VIL <= 40% of VIF |
| HIGH level input voltage (VIH) | VIH >= 60% of VIF |
| For 1.2V >= VIF <= 3.6V | |
| LOW level output voltage (VOL) with a load of 10 kOhm | VOL <= 10% of VIF |
| HIGH level output voltage (VOH) with a load of 10 kOhm | VOH >= 90% of VIF |
| For 3.6 <= VIF <= 5V | |
| LOW level output voltage (VOL) with a load of 10 kOhm | VOL <= 20% of VIF |
| HIGH level output voltage (VOH) with a load of 10 kOhm | VOH >= 80% of VIF |
| JTAG/SWD Interface, Timing | |
| Target interface speed | Max. 15 MHz |
| SWO sampling frequency | Max. 30 MHz |
| Data input rise time (Trdi) | Trdi <= 20ns |
| Data input fall time (Tfdi) | Tfdi <= 20ns |
| Data output rise time (Trdo) | Trdo <= 10ns |
| Data output fall time (Tfdo) | Tfdo <= 10ns |
| Clock rise time (Trc) | Trc <= 3ns |
| Clock fall time (Tfc) | Trc <= 3ns |
J-Link BASE Compact Assembly
J-Link BASE Compact explosion view
J-Link BASE Compact dimensions
The compact variant of the J-Link BASE is designed to mount securely and unobtrusively into development or end user equipment. The small size and two mounting holes enable placing the J-Link BASE Compact into existing equipment housings or to reserve space for direct-to-PCB mounting.
Typical applications are test fixtures that are used to automate firmware verification during development, or long-term test setups. It also can be used for integrated firmware reflash or service purposes inside end equipment, minimizing the number of tools that service technicians must carry around.
Package Content
J-Link BASE
J-Link BASE
.1" 20-pin ribbon cable
USB cable
J-Link BASE Compact
J-Link BASE Compact
.1" 20-pin ribbon cable
Micro USB cable