J-Link ULTRA+
- Download speed up to 3 MByte/s
- Additional LEDs for power and RESET indication
- 2 years of email support (J-Link BASE/PLUS: 1 year)
- Superset of J-Link PLUS [More..]
- Comes with integrated licenses for: Unlimited breakpoints in flash memory (Unlimited Flash Breakpoints), RDI / RDDI and J-Flash
- Supports a broad range of microcontrollers: [More..]
- Supports direct download into RAM and flash memory
- Multiple CPUs supported—8051, PIC32, RX, ARM7/9/11, Cortex-M/R/A, RISC-V [More..]
- Free software updates
- Built-in VCOM functionality [More..]
J-Link ULTRA+ is an ultra fast debug probe for JTAG/SWD. It is 100% compatible with J-Link PLUS, just faster. Unplug your J-Link PLUS, plug in your J-Link ULTRA+ and enjoy the faster download speeds. It simply works!
J-Link ULTRA+ is a JTAG/SWD debug probe designed for ARM/Cortex. It is fully compatible to the standard J-Link and works with the same PC software.
Based on the highly optimized and proven J-Link, it offers even higher speed as well as target power measurement capabilities due to the faster CPU, built-in FPGA and High speed USB interface.
| Specification | Value | ||||
|---|---|---|---|---|---|
| Supported OS | Microsoft Windows 2000, XP, 2003, Vista, 7 and newer (32 bit and 64 bit versions) Linux macOS 10.5 and higher | ||||
| Electromagnetic compatibility (EMC) | EN 55022, EN 55024 | ||||
| Operating temperature | +5°C ... +60°C | ||||
| Storage temperature | -20°C ... +65 °C | ||||
| Relative humidity (non-condensing) | Max. 90% rH | ||||
| Mechanical | |||||
| Size (without cables) | 100mm x 53mm x 27mm | ||||
| Weight (without cables) | 73g | ||||
| Available Interfaces | |||||
| USB interface | USB 2.0, (Hi-Speed) | ||||
| Target interface | JTAG/SWD 20-pin | ||||
| JTAG/SWD Interface, Electrical | |||||
| Target interface voltage (VIF) | 1.2V ... 5V | ||||
| Current drawn from target voltage sense pin (VTRef) | < 25µA | ||||
| Target supply voltage | 5V (derived from USB voltage) | ||||
| Target supply current | Max. 300mA | ||||
| Reset type | Open drain. Can be pulled low or tristated | ||||
| Reset low level output voltage | VOL <= 10% of VIF | ||||
| For the whole target voltage range (1.2V <= VIF <= 5V) | |||||
| LOW level input voltage (VIL) | VIL <= 40% of VIF | ||||
| HIGH level input voltage (VIH) | VIH >= 60% of VIF | ||||
| For 1.2V >= VIF <= 3.6V | |||||
| LOW level output voltage (VOL) with a load of 10 kOhm | VOL <= 20% of VIF | ||||
| HIGH level output voltage (VOH) with a load of 10 kOhm | VOH >= 80% of VIF | ||||
| For 3.6 <= VIF <= 5V | |||||
| LOW level output voltage (VOL) with a load of 10 kOhm | VOL <= 20% of VIF | ||||
| HIGH level output voltage (VOH) with a load of 10 kOhm | VOH >= 80% of VIF | ||||
| JTAG/SWD Interface, Timing | |||||
| Target interface speed | Max. 50 MHz | ||||
| SWO sampling frequency | Max. 100 MHz | ||||
| Data input rise time (Trdi) | Trdi <= 20ns | ||||
| Data input fall time (Tfdi) | Tfdi <= 20ns | ||||
| Data output rise time (Trdo) | Trdo <= 10ns | ||||
| Data output fall time (Tfdo) | Tfdo <= 10ns | ||||
| Clock rise time (Trc) | Trc <= 3ns | ||||
| Clock fall time (Tfc) | Trc <= 3ns | ||||
| Analog power measurement interface | |||||
| Sampling frequency | 200 kHz | ||||
| Resolution | 50 uA | ||||
