Overview of Supported CPUs and Devices
Any microcontroller, MPU, SoC with a supported CPU core with its debug interface accessible is supported and can be fully controlled by J-Link.
ARM Cortex
Cortex-A/R 64-bit
- Cortex-A53
- Cortex-A72
Cortex-A/R 32-bit
- Cortex-A5
- Cortex-A7
- Cortex-A8
- Cortex-A9
- Cortex-A12
- Cortex-A15
- Cortex-A17
- Cortex-R4
- Cortex-R5
- Cortex-R8
Cortex-M
- Cortex-M0
- Cortex-M0+
- Cortex-M1
- Cortex-M3
- Cortex-M4
- Cortex-M7
- Cortex-M23
- Cortex-M33
- Cortex-M55
ARM China
- Star
RISC-V
RV32
- AndesTech A25
- CloudBEAR BM-310
- Codasip L10
- Codasip L30
- Codasip L30F
- Codasip L50
- Codasip L50F
- SiFive E21
- SiFive E24
- SiFive E31
- SiFive E34
- SiFive E76
RV64
- CloudBEAR BM-610
- Codasip H50X
- Codasip H50XF
- SiFive S21
- SiFive S51
- SiFive S54
- SiFive S76
Renesas RX
- Renesas RX110
- Renesas RX111
- Renesas RX113
- Renesas RX130
- Renesas RX210
- Renesas RX21A
- Renesas RX220
- Renesas RX231
- Renesas RX23T
- Renesas RX24T
- Renesas RX610
- Renesas RX621
- Renesas RX62G
- Renesas RX62N
- Renesas RX62T
- Renesas RX630
- Renesas RX631
- Renesas RX63N
- Renesas RX63T
- Renesas RX64M
- Renesas RX65N
- Renesas RX651
- Renesas RX66T
- Renesas RX71M
- Renesas RX72M
- Renesas RX72N
- Renesas RX72T
Microchip PIC
- Microchip PIC32MX
- Microchip PIC32MZ
- Microchip PIC32WK
Silicon Labs 8051
- EFM8
ARM (legacy cores)
- ARM720T
- ARM7TDMI
- ARM7TDMI-S
- ARM920T
- ARM922T
- ARM926EJ-S
- ARM946E-S
- ARM966E-S
- ARM1136JF-S
- ARM1136J-S
- ARM1156T2-S
- ARM1156T2F-S
- ARM1176JZ-S
- ARM1176JZF
- ARM1176JZF-S
Known Devices
Known devices are supported devices which are also known by name. Knowing not just the CPU core, but also the device by name brings the following advantages:
- Programming of internal flash (See Flash Download)
- Availability of unlimited number of breakpoints in flash memory (See Flash Breakpoints)
- Known memory map allows speed optimizations for access to Flash and RAM
- Support for non-standard CPU-cores & bugs in silicon: Some silicon requires special sequences for unlock, reset, or simply connecting to the core. For known devices, this is implemented
Note that a device has not to be known by name to be supported. This means that J-Link can be used with any device, using a standard core listed in the table of supported CPU cores even if it is known by name.
List of Known Devices
The following list gives an overview about which devices are known by J-Link. Note that your device may still be supported even if it is not in this list, as long as it incorporates a core that is listed in Supported CPU Cores. In case of doubt, please feel free to get in touch with SEGGER.
The list from below is always valid for the latest version (highest version number) of the J-Link/Flasher software package. This may be a release (even version number) or beta version (odd version number), since support for some devices is usually added in a beta phase first.
Adding support for new/unknown devices
If a device is not listed in the list of known devices on this page, there are two options to get it to be known by J-Link:
- Adding support for it (incl. flash programming) on your own. For more information on how to do this, please refer to the SEGGER wiki.
- Get in touch with support@segger.com and issue a device support request
Note that a device has not to be known by name to be supported. This means that J-Link can be used with any device, using a standard core listed in Supported CPU Cores even if it is known by name.
Supported SPI flashes
J-Link does also support download into SPIFI (SPI Flash Interface) flashes in case they are memory mapped readable through the CPU (called SPIFI support on most targets). Moreover, utilities like J-Flash SPI also support direct programming of SPI flashes without any CPU in between. The following SPI flashes are currently supported by the J-Link software.
