The Universal Debug Probe
J-Link PRO is a refined version of the regular J-Link. It has an Ethernet interface in addition to the USB interface, as well as two additional LEDs which are used as hardware status indicators. It connects via Ethernet or USB to the host, running Windows, Linux or macOS.
- Additional Ethernet interface
- Download speed up to 3 MByte/s
- Superset of J-Link ULTRA+
About J-Link PRO
J-Link PRO is fully compatible with J-Link and can be used "out-of-the-box". J-Link PRO uses DHCP per default. The built-in webserver makes manual configuration easy. Ethernet allows using the debug probe far away from the PC, over a hardwired or wireless network, in a development or production environment; download and debugging speed is higher and Ethernet provides electrical isolation from the PC. All features of the regular J-Link also apply to this product.
Why Use J-Link PRO?
Further Advantages
- Comes with web interface for easy TCP/IP configuration (built-in webserver)
- Built-in VCOM functionality
- 2 years of email support (J-Link BASE/PLUS: 1 year)
- Comes with integrated licenses for: Unlimited breakpoints in flash memory
(Unlimited Flash Breakpoints), RDI / RDDI and J-Flash - Supports a broad range of microcontrollers
- Multiple CPUs supported—8051, PIC32, RX, ARM7/9/11, Cortex-M/R/A, RISC-V [More..]
- Supports direct download into RAM and flash memory
- Free software updates
- Additional LEDs for power and RESET indication
J-Link PRO Licensing
J-Link PRO comes with licenses for all J-Link related SEGGER software products: J-Link Unlimited Flash Breakpoints, J-Link RDI / RDDI, J-Flash, J-Link GDB Server, providing the optimum debugging solution for professional developers.
J-Link PRO can be used with almost all ARM debuggers, enabling download to flash memory with an unlimited number of breakpoints when debugging programs located in flash memory of most popular ARM microcontrollers. It also comes with the license to use J-Flash, SEGGER's popular flash programming software.
SEGGER J-Link Flash Breakpoint Introduction
SEGGER J-Flash Introduction
J-Link PRO Specifications
| General | ||||||||
|---|---|---|---|---|---|---|---|---|
| Supported OS | Microsoft Windows 2000, XP, 2003, Vista, 7 and newer (32 bit and 64 bit versions) Linux macOS 10.5 and higher | |||||||
| Electromagnetic compatibility (EMC) | EN 55022, EN 55024 | |||||||
| Operating temperature | +5°C ... +60°C | |||||||
| Storage temperature | -20°C ... +65 °C | |||||||
| Relative humidity (non-condensing) | Max. 90% rH | |||||||
| Mechanical | ||||||||
| Size (without cables) | 100mm x 53mm x 27mm | |||||||
| Weight (without cables) | 73g | |||||||
| Available Interfaces | ||||||||
| Ethernet interface | 100 Mbit/s | |||||||
| USB interface | USB 2.0 (Hi-Speed) | |||||||
| Target interface | JTAG/SWD 20-pin | |||||||
| JTAG/SWD Interface, Electrical | ||||||||
| Target interface voltage (VIF) | 1.2V ... 5V | |||||||
| Current drawn from target voltage sense pin (VTRef) | < 25µA | |||||||
| Target supply voltage | 5V (derived from USB voltage) | |||||||
| Target supply current | Max. 300mA | |||||||
| Reset type | Open drain. Can be pulled low or tristated | |||||||
| Reset low level output voltage | VOL <= 10% of VIF | |||||||
| For the whole target voltage range (1.2V <= VIF <= 5V) | ||||||||
| LOW level input voltage (VIL) | VIL <= 40% of VIF | |||||||
| HIGH level input voltage (VIH) | VIH >= 60% of VIF | |||||||
| For 1.2V >= VIF <= 3.6V | ||||||||
| LOW level output voltage (VOL) with a load of 10 kOhm | VOL <= 20% of VIF | |||||||
| HIGH level output voltage (VOH) with a load of 10 kOhm | VOH >= 80% of VIF | |||||||
| For 3.6 <= VIF <= 5V | ||||||||
| LOW level output voltage (VOL) with a load of 10 kOhm | VOL <= 20% of VIF | |||||||
| HIGH level output voltage (VOH) with a load of 10 kOhm | VOH >= 80% of VIF | |||||||
| JTAG/SWD Interface, Timing | ||||||||
| Target interface speed | Max. 50 MHz | |||||||
| SWO sampling frequency | Max. 100 MHz | |||||||
| Data input rise time (Trdi) | Trdi <= 20ns | |||||||
| Data input fall time (Tfdi) | Tfdi <= 20ns | |||||||
| Data output rise time (Trdo) | Trdo <= 10ns | |||||||
| Data output fall time (Tfdo) | Tfdo <= 10ns | |||||||
| Clock rise time (Trc) | Trc <= 3ns | |||||||
| Clock fall time (Tfc) | Trc <= 3ns | |||||||
| Analog power measurement interface | ||||||||
| Sampling frequency | 200 kHz | |||||||
| Resolution | 50 uA | |||||||
