JTAG/SWD debug probe with USB interface
J-Link BASE is a USB powered JTAG debug probe supporting a large number of CPU cores.
Based on a 32-bit RISC CPU, it can communicate at high speed with the supported target CPUs. J-Link is used around the world in tens of thousand places for development and production (flash programming) purposes.
J-Link is supported by all major IDEs such as IAR EWARM, Keil MDK, Rowley CrossWorks, Atollic TrueSTUDIO, IAR EWRX, Renesas HEW, Renesas e2studio, and many others.
Including all models, more than 100,000 J-Links have been sold so far, making J-Link probably the most popular debug probe for ARM cores and the de-facto standard.
- Direct download into flash memory of most popular microcontrollers supported
- Supported CPUs: ARM7/9/11, Cortex-A5/A7/A8/A9, Cortex-M0/M1/M3/M4/M7, Cortex-R4/R5, Microchip PIC32 and Renesas RX100/RX200/RX610/RX621/RX62N/RX62T/RX630/RX631/RX63N
- Download speed up to 1 MByte/second
- Supports unlimited breakpoints in flash memory!1 More info...
- Setting breakpoints in external flash memory of Cortex-M systems is possible with
J-Link's Unlimited Flash Breakpoints technology only!
- Supported by all major IDEs More info...
- Free software updates2, 1 year of support
- Supports concurrent access to CPU by multiple applications3
- Crossplatform support (runs on Windows, Linux, Mac OS X)4
- Intelligence in the debug probe firmware More info...
- Remote Server included. Allows using J-Link remotely via TCP/IP More info...
- GDBServer included More info...
- Production flash programming software (J-Flash) available More info...
- Software Developer Kit (SDK) available More info...
- Supports multiple target interfaces: JTAG, SWD
- Supports SWV/SWO (Serial Wire Viewer / Serial wire output)
- Wide target voltage range: 1.2V - 3.3V, 5V tolerant
- Supports JTAG chains with multiple devices
- Embedded Trace Buffer (ETB) support
- Various target adapters and optical isolation adapters available.
- RDI / RDDI interface DLL available. More info...
- Fully plug and play compatible
- No power supply required, powered through USB
- Support for adaptive clocking
- All JTAG signals can be monitored, target voltage can be measured
- Target power supply: J-Link can supply up to 300 mA to target with overload protection
More information about J-Link...
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1The unlimited breakpoints in flash memory feature can be used free of charge for evaluation. The evaluation period is not time limited. For commercial use a separate license is required.
2As a legitimate owner of a SEGGER J-Link, you can always download the latest software free of charge. Though not planned and not likely, we reserve the right to change this policy. Note that older models may not be supported by newer versions of the software. Typically, we support older models with new software at least 3 years after end of life.
3J-Link allows multiple applications to access a CPU at the same time. This has numerous applications. J-Link commander can be used in parallel to a debugger, a tool to communicate via DCC can be used in parallel to a debugger or a visualization tool such as Micrium's u/C-Probe or SEGGER's kernel viewer embOSView. This feature is currently not available for Cortex A and R cores.
4The MAC and Linux versions are fully usable, but limited to the following components:
J-Link Commander, command line GDBServer, shared library (DLL-equivalent).
|Supported OS||Microsoft Windows 2000
Microsoft Windows XP
Microsoft Windows XP x64
Microsoft Windows 2003
Microsoft Windows 2003 x64
Microsoft Windows Vista
Microsoft Windows Vista x64
Microsoft Windows 7
Microsoft Windows 7 x64
Microsoft Windows 8
Microsoft Windows 8 x64
Microsoft Windows 10
Microsoft Windows 10 x64
Mac OSX 10.5 and higher
|Electromagnetic compatibility (EMC)||EN 55022, EN 55024|
|Operating temperature||+5°C ... +60°C|
|Storage temperature||-20°C ... +65 °C|
|Relative humidity (non-condensing)||Max. 90% rH|
|Size (without cables)||100mm x 53mm x 27mm|
|Weight (without cables)||70g|
|USB interface||USB 2.0|
|Target interface||JTAG 20-pin (14-pin adapter available)|
|JTAG/SWD Interface, Electrical|
|Power supply||USB powered
Max. 50mA + Target Supply current.
|Target interface voltage (VIF)||1.2V ... 5V|
|Current drawn from target voltage sense pin (VTRef)||< 25µA|
|Target supply voltage||4.5V ... 5V (if powered with 5V on USB)|
|Target supply current||Max. 300mA|
|Reset Type||Open drain. Can be pulled low or
|Reset low level output voltage (VOL)||VOL <= 10% of VIF|
|For the whole target voltage range (1.2V <= VIF <= 5V)|
|LOW level input voltage (VIL)||VIL <= 40% of VIF|
|HIGH level input voltage (VIH)||VIH >= 60% of VIF|
|For 1.2V <= VIF <= 3.6V|
|LOW level output voltage (VOL) with a load of 10 kOhm||VOL <= 10% of VIF|
|HIGH level output voltage (VOH) with a load of 10 kOhm||VOH >= 90% of VIF|
|For 3.6 <= VIF <= 5V|
|LOW level output voltage (VOL) with a load of 10 kOhm||VOL <= 20% of VIF|
|HIGH level output voltage (VOH) with a load of 10 kOhm||VOH >= 80% of VIF|
|JTAG/SWD Interface, Timing|
|JTAG speed||Max. 15MHz|
|SWO sampling frequency||Max. 7.5MHz|
|Data input rise time (Trdi)||Trdi <= 20ns|
|Data input fall time (Tfdi)||Tfdi <= 20ns|
|Data output rise time (Trdo)||Trdo <= 10ns|
|Data output fall time (Tfdo)||Tfdo <= 10ns|
|Clock rise time (Trc)||Trc <= 3ns|
|Clock fall time (Tfc)||Tfc <= 3ns|
* J-Link hardware revision 8 and up