SEGGER - Jobs
emWin upgrade     Trade-In program     Web shop

J-Trace for Cortex-M

JTAG debug probe with trace support for Cortex-M cores

J-Trace for Cortex-M is a JTAG debug probe designed for Cortex-M cores which includes trace (ETM) support. J-Trace for Cortex-M can also be used as a J-Link. 

Features

  • Has all the J-Link functionality
  • Hi-Speed-USB 2.0 interface
  • JTAG speed: 25 MHz
  • Works with all currently available Cortex-M devices at 100 MHz trace clock
  • Supports Cortex-M0/M0+/M1/M3/M4/M7 targets
  • Supports ARM's Embedded Trace Macrocell (ETM)
  • Supports ARM's Embedded Trace Buffer (ETB)
  • Supports ARM's Micro Trace Buffer (MTB)
  • Free software updates1, 2 years of support
  • 16 MB trace buffer

1As a legitimate owner of a SEGGER J-Trace, you can always download the latest software free of charge. Though not planned and not likely, we reserve the right to change this policy. Note that older models may not be supported by newer versions of the software. Typically, we support older models with new software at least 3 years after end of life.


A new version of J-Trace Cortex-M is available: J-Trace PRO for Cortex-M

J-Trace PRO advantages include streaming trace with live code analysis (code coverage and profiling) and unlimited recording. No trace buffer limit!

Exchange your J-Trace with a J-Trace PRO using the SEGGER Trade-In Program




Package content

J-Trace Cortex-M is delivered with the following components:
J-Trace Cortex-M .05" 20-pin trace cable .1" 20-pin ribbon cable USB cable


19-pin JTAG/SWD and Trace connector

J-Trace provides a JTAG/SWD+Trace connector. This connector is a 19-pin connector. It connects to the target via an 1-1 cable. The following table lists the J-Link / J-Trace SWD pinout.
Pin Signal Type Description
1 VTref Input This is the target reference voltage. It is used to check if the target has power, to create the logic-level reference for the input comparators and to control the output logic levels to the target. It is normally fed from Vdd of the target board and must not have a series resistor.
2 SWDIO/ TMS I/O / output JTAG mode set input of target CPU. This pin should be pulled up on the target. Typically connected to TMS of the target CPU.
4 SWCLK/TCK Output JTAG clock signal to target CPU. It is recommended that this pin is pulled to a defined state of the target board. Typically connected to TCK of the target CPU.
6 SWO / TDO Input JTAG data output from target CPU. Typically connected to TDO of the target CPU.
--- --- --- This pin (normally pin 7) is not existent on the 19-pin JTAG/SWD and Trace connector.
8 TDI Output JTAG data input of target CPU.- It is recommended that this pin is pulled to a defined state on the target board. Typically connected to TDI of the target CPU.
9 NC NC Not connected inside J-Link. Leave open on target hardware.
10 nRESET I/O Target CPU reset signal. Typically connected to the RESET pin of the target CPU, which is typically called "nRST", "nRESET" or "RESET".
11 5V-Supply Output This pin can be used to supply power to the target hardware. For more information about how to enable/disable the power supply, please refer to Target power supply on page 142.
12 TRACECLK Input Input trace clock. Trace clock = 1/2 CPU clock.
13 5V-Supply Output This pin can be used to supply power to the target hardware. For more information about how to enable/disable the power supply, please refer to Target power supply on page 142.
14 TRACEDATA[0] Input Input Trace data pin 0.
16 TRACEDATA[1] Input Input Trace data pin 1.
18 TRACEDATA[2] Input Input Trace data pin 2.
20 TRACEDATA[3] Input Input Trace data pin 3.

Specifications

General
Supported OS
Microsoft Windows 2000
Microsoft Windows XP
Microsoft Windows XP x64
Microsoft Windows 2003
Microsoft Windows 2003 x64
Microsoft Windows Vista
Microsoft Windows Vista x64
Microsoft Windows 7
Microsoft Windows 7 x64
Microsoft Windows 8
Microsoft Windows 8 x64
Microsoft Windows 10
Microsoft Windows 10 x64
Linux
Mac OSX 10.5 and higher
Electromagnetic compatibility (EMC) EN 55022, EN 55024
Operating temperature +5°C ... +60°C
Storage temperature -20°C ... +65 °C
Relative humidity (non-condensing) Max. 90% rH
Size (without cables) 123mm x 68mm x 30mm
Weight (without cables) 120g
Mechanical
USB interface USB 2.0, Hi-Speed
Target interface JTAG/SWD 20-pin (14-pin adapter available)
JTAG/SWD + Trace 19-pin
JTAG/SWD Interface, Electrical
Power supply USB powered
Max. 50mA + Target Supply current.
Target interface voltage (VIF) 1.2V ... 5V
Target supply voltage 4.5V ... 5V (if powered with 5V on USB)
Target supply current Max. 300mA
LOW level input voltage (VIL) Max. 40% of VIF
HIGH level input voltage (VIH) Min. 60% of VIF
JTAG/SWD Interface, Timing
Data input rise time (Trdi) Max. 20ns
Data input fall time (Tfdi) Max. 20ns
Data output rise time (Trdo) Max. 10ns
Data output fall time (Tfdo) Max. 10ns
Clock rise time (Trc) Max. 10ns
Clock fall time (Tfc) Max. 10ns
Trace Interface, Electrical
Power supply USB powered
Max. 50mA + Target Supply current.
Target interface voltage (VIF) 1.2V ... 5V
Voltage interface low pulse (VIL) Max. 40% of VIF
Voltage interface high pulse (VIH) Min. 60% of VIF
Trace Interface, Timing
TRACECLK low pulse width (Twl) Min. 2ns
TRACECLK high pulse width (Twh) Min. 2ns
Data rise time (Trd) Max. 3ns
Data fall time (Tfd) Max. 3ns
Clock rise time (Trc) Max. 3ns
Clock fall time (Tfc) Max. 3ns
Data setup time (Ts) Min. 3ns
Data hold time (Th) Min. 2ns