J-Trace PRO for Cortex-M—The Leading Trace Probe
- Trace and streaming probe
- Real-time streaming of events and system ticks
- Tune your application with live profiling
- Satisfy regulatory requirements with instruction-level code coverage
- Isolate and Identify hard-to-find code defects with unlimited trace
- Supports Streaming Trace [More..]
- Supports Cortex-M microcontroller [More..]
- Full J-Link debug functionality [More..]
J-Trace PRO for Cortex-M is setting a new standard for trace probes. It enables continuous streaming trace, lifting the limitations by internal buffers and slow data transmission to give you all the insights you need to develop and optimize your code.
J-Trace PRO can capture complete traces over long periods—thereby enabling the recording of infrequent, hard-to-reproduce bugs. This is particularly helpful when the program flow ‘runs off the rails’ and stops in a fault state.
It also supports extended trace features, such as code coverage (so engineers have visibility over which parts of the application code have been executed) and execution profiling (providing visibility as to which instructions have been executed and how often—so hotspots can be addressed and optimization opportunities identified).
| Specification | Value | |||||||
|---|---|---|---|---|---|---|---|---|
| Supported OS | Microsoft Windows 2000 Microsoft Windows XP Microsoft Windows XP x64 Microsoft Windows 2003 Microsoft Windows 2003 x64 Microsoft Windows Vista Microsoft Windows Vista x64 Microsoft Windows 7 Microsoft Windows 7 x64 Microsoft Windows 8 Microsoft Windows 8 x64 Microsoft Windows 10 Microsoft Windows 10 x64 Linux macOS 10.5 and higher | |||||||
| Electromagnetic compatibility (EMC) | EN 55022, EN 55024 | |||||||
| Operating temperature | +5°C ... +60°C | |||||||
| Storage temperature | -20°C ... +65 °C | |||||||
| Relative humidity (non-condensing) | Max. 90% rH | |||||||
| Mechanical | ||||||||
| Size (without cables) | 123mm x 68mm x 30mm | |||||||
| Weight (without cables) | (without cables) 120g | |||||||
| Available Interfaces | ||||||||
| Ethernet interface | Gigabit | |||||||
| USB interface | USB 3.0, SuperSpeed | |||||||
| Target interface | JTAG/SWD 20-pin (14-pin adapter available) JTAG/SWD + Trace 19-pin | |||||||
| JTAG/SWD Interface, Electrical | ||||||||
| Power supply | USB powered (max. 400mA) | |||||||
| Target interface voltage (VIF) | 1.2V ... 5V | |||||||
| LOW level input voltage (VIL) | VIL <= 40% of VIF | |||||||
| HIGH level input voltage (VIH) | VIH >= 60% of VIF | |||||||
| JTAG/SWD Interface, Timing | ||||||||
| Data input rise time (Trdi) | Max. 20ns | |||||||
| Data input fall time (Tfdi) | Max. 20ns | |||||||
| Data output rise time (Trdo) | Max. 10ns | |||||||
| Data output fall time (Tfdo) | Max. 10ns | |||||||
| Clock rise time (Trc) | Max. 10ns | |||||||
| Clock fall time (Tfc) | Max. 10ns | |||||||
| Trace Interface, Electrical | ||||||||
| Power supply | USB powered (max. 400mA) | |||||||
| Target interface voltage (VIF) | 1.2V ... 5V | |||||||
| Voltage interface low pulse (VIL) | Max. 40% of VIF | |||||||
| Voltage interface high pulse (VIH) | Min. 60% of VIF | |||||||
| Trace Interface, Timing | ||||||||
| TRACECLK low pulse width (Twl) | Max. 2ns | |||||||
| TRACECLK high pulse width (Twh) | Max. 2ns | |||||||
| Data rise time (Trd) | Max. 3ns | |||||||
| Data fall time (Tfd) | Max. 3ns | |||||||
| Clock rise time (Trc) | Max. 3ns | |||||||
| Clock fall time (Tfc) | Max. 3ns | |||||||
19-Pin JTAG/SWD and Trace Connector
J-Trace provides a JTAG/SWD+Trace connector. This connector is a 19-pin connector. It connects to the target via a 1-1 cable. The following table lists the J-Link / J-Trace SWD pinout.
| Signal | Type | Description | |
|---|---|---|---|
| Pin 1 | VTref | Input | This is the target reference voltage. It is used to check if the target has power, to create the logic-level reference for the input comparators and to control the output logic levels to the target. It is normally fed from Vdd of the target board and must not have a series resistor. |
| Pin 2 | SWDIO/ TMS | I/O / output | JTAG mode set input of target CPU. This pin should be pulled up on the target. Typically connected to TMS of the target CPU. |
| Pin 4 | SWCLK/TCK | Output | JTAG clock signal to target CPU. It is recommended that this pin is pulled to a defined state of the target board. Typically connected to TCK of the target CPU. |
| 6 | SWO / TDO | Input | JTAG data output from target CPU. Typically connected to TDO of the target CPU. |
| --- | --- | --- | This pin (normally pin 7) is not existent on the 19-pin JTAG/SWD and Trace connector. |
| Pin 8 | TDI | Output | JTAG data input of target CPU.- It is recommended that this pin is pulled to a defined state on the target board. Typically connected to TDI of the target CPU. |
| Pin 9 | NC | NC | Not connected inside J-Link. Leave open on target hardware. |
| Pin 10 | nRESET | I/O | Target CPU reset signal. Typically connected to the RESET pin of the target CPU, which is typically called "nRST", "nRESET" or "RESET". |
| Pin 12 | TRACECLK | Input | Input trace clock. Trace clock = 1/2 CPU clock. |
| Pin 14 | TRACEDATA[0] | Input | Input Trace data pin 0. |
| Pin 16 | TRACEDATA[1] | Input | Input Trace data pin 1. |
| Pin 18 | TRACEDATA[2] | Input | Input Trace data pin 2. |
| Pin 20 | TRACEDATA[3] | Input | Input Trace data pin 3. |
