Skip to main content
  • Products
  • Evaluate our Software
  • Downloads
  • Free Utilities
  • Purchase
  • Silicon Vendors
  • Support
  • About Us
  • Blog
  • Forum
  • Search
  • Jobs
  • Newsletter
  • Blog
  • Contact
  • Shop
  • J-Link debug probes
  • RX Adapter

    RX Adapter

    The RX Adapter allows connections between J-Link or Flasher and target hardware which comes with the Renesas RX600 / 200 / 100 series MCUs.

    Buy now
    Compare J-Link adapters
    Documentation
    SEGGER Debug & Trace Probes
    1. 1.Pinouts and Jumper Settings
      1. 1.1.JTAG Connection
      2. 1.2.FINE Connection
    2. 2.CPU Signal <-> RX Adapter Connection
    3. 3.Schematics

    Overview

    The RX Adapter allows connections between J-Link or Flasher and target hardware which comes with the Renesas RX600 / 200 / 100 series MCUs. When using the RX Adapter, please make sure that you are using the latest revision of this adapter, since on older revisions specific features like FINE interface support may not be supported. The back-side of the adapter shows the revision of it. The current revision is 5. Older revisions may not show a revision on the back-side but a production date only. Please replace these adapters with one of revision 5 or newer.

    The RX adapter is able to optionally power the connected target hardware. 3.3 V or 5 V supply voltage can be selected using a Jumper. The target is supplied via the VTref connection (pin 8) when the supply option is jumpered. The RX Adapter is shipped with option "do not power target" (jumper open)

    RX Adapter
    RX Adapter
    RX Adapter with cable
    RX Adapter with cable

    Pinouts and Jumper Settings

    JTAG Connection

    RX Adapter Pinout — JTAG connection
    RX Adapter Pinout — JTAG connection
    Jumper (light red) setting – JTAG connection
    Jumper (light red) setting – JTAG connection

    The RX Adapter supports connecting via JTAG to the following cores:

    • RX610
    • RX621
    • RX62G
    • RX62N
    • RX62T
    • RX630
    • RX631
    • RX63N
    • RX63T
    • RX64M
    • RX65N
    • RX660
    • RX66T
    • RX671
    • RX71M
    • RX72N

    FINE Connection

    RX Adapter Pinout — FINE connection
    RX Adapter Pinout — FINE connection
    Jumper (light red) setting – FINE connection
    Jumper (light red) setting – FINE connection

    It can also be used for connecting via FINE to the following cores:

    • RX111
    • RX13T
    • RX140
    • RX210
    • RX21A
    • RX220

    Please note:
    For connecting to RX63x or RX72N devices via FINE, the RX FINE Adapter is required.

    The FINED Signal: Since the FINE interface is a open-drain specified interface, there is always a pull-up necessary on the target hardware. Pull-up recommendation is 1k Ohm.

    CPU Signal <-> RX Adapter Connection

    TDTDI In the following, for the different Renesas RX CPUs the CPU signal <-> J-Link RX Adapter signal mapping is described.

    RX111 CPUs:

    The following table shows the mapping for FINE. This core does not support JTAG.

     

    FINE 
    CPU signal / pin nameRX Adapter pin / signal name
    FINEC / P27Pin 1 (FINEC)
    NCPin 4 (EMLE)
    MD_FINED (via pull-up)Pin 7 (FINED)
    P14Pin 10 (UB)
    RESnPin 13 (nRES)

     

    RX210 CPUs:

    The following table shows the mapping for FINE. This core does not support JTAG.

    FINE 
    CPU signal / pin nameRX Adapter pin / signal name
    SCK1 / P27Pin 1 (FINEC)
    NCPin 4 (EMLE)
    MODE / MD_FINED (via pull-up)Pin 7 (FINED)
    UB / PC7Pin 10 (UB)
    RESET_N / nRESPin 13 (nRES)

     

    RX220 CPUs:

    The following table shows the mapping for FINE. This core does not support JTAG.

    FINE 
    CPU signal / pin nameRX Adapter pin / signal name
    SCK1 / P27Pin 1 (FINEC)
    NCPin 4 (EMLE)
    MODE / MD_FINED (via pull-upPin 7 (FINED)
    UB / PC7Pin 10 (UB)
    RESET_N / nRESPin 13 (nRES)

     

    RX630 CPUs:

    This core supports FINE and JTAG. The following table shows the mapping for JTAG.
    To operate the FINE interface of this core please use the RX FINE Adapter.

    JTAG 
    CPU signal / pin nameRX Adapter pin / signal name
    P27 / TCK / FINECPin 1 (TCK)
    TRSTnPin 3 (nTRST)
    EMLEPin 4 (EMLE)
    TDOPin 5 (TDO)
    MD_FINED (via pull-up)Pin 7 (MD0)
    TMSPin 9 (TMS)
    IRQ14 / PC7Pin 10 (UB)
    TDIPin 11 (TDI)
    RESnPin 13 (nRES)

     

    RX631 / RX63N CPUs:

    This core supports FINE and JTAG. The following table shows the mapping for JTAG.
    To operate the FINE interface of this core please use the RX FINE Adapter.

    JTAG 
    CPU signal / pin nameRX Adapter pin / signal name
    P27 / TCK / FINECPin 1 (TCK)
    TRSTnPin 3 (nTRST)
    EMLEPin 4 (EMLE)
    TDOPin 5 (TDO)
    MD_FINED (via pull-up)Pin 7 (MD0)
    TMSPin 9 (TMS)
    IRQ14 / PC7Pin 10 (UB)
    TDIPin 11 (TDI)
    RESnPin 13 (nRES)

     

    RX63T CPUs:

    This core supports FINE and JTAG. The following table shows the mapping for JTAG.
    To operate the FINE interface of this core please use the RX FINE Adapter.

     

    JTAG 
    CPU signal / pin nameRX Adapter pin / signal name
    P27 / TCK / FINECPin 1 (TCK)
    TRSTnPin 3 (nTRST)
    EMLEPin 4 (EMLE)
    TDOPin 5 (TDO)
    MD_FINED (via pull-up)Pin 7 (MD0)
    TMSPin 9 (TMS)
    IRQ14 / PC7Pin 10 (UB)
    TDIPin 11 (TDI)
    RESnPin 13 (nRES)

     

    RX671 CPUs:

    This core supports FINE and JTAG. The following table shows the mapping for JTAG.
    To operate the FINE interface of this core please use the RX FINE Adapter.

    JTAG 
    CPU signal / pin nameRX Adapter pin / signal name
    TCKPin 1 (TCK)
    TRSTnPin 3 (nTRST)
    EMLEPin 4 (EMLE)
    TDOPin 5 (TDO)
    MD (via pull-up)Pin 7 (MD0)
    TMSPin 9 (TMS)
    UBPin 10 (UB)
    TDIPin 11 (TDI)
    RESnPin 13 (nRES)

     

    RX72N CPUs:

    This core supports FINE and JTAG. The following table shows the mapping for JTAG.
    To operate the FINE interface of this core please use the RX FINE Adapter.

    JTAG 
    CPU signal / pin nameRX Adapter pin / signal name
    TCKPin 1 (TCK)
    TRSTnPin 3 (nTRST)
    EMLEPin 4 (EMLE)
    TDOPin 5 (TDO)
    MD (via pull-up)Pin 7 (MD0)
    TMSPin 9 (TMS)
    UBPin 10 (UB)
    TDIPin 11 (TDI)
    RESnPin 13 (nRES)

    Schematics

    The following functional block diagram illustrates the connections between the debug probe and the target.

    RX Adapter Block Diagram
    RX Adapter Block Diagram

    Suitable products

    • J-Link Pro PoE
    • J-Link Pro
    • J-Link ULTRA+
    • J-Link WiFi
    • J-Link PLUS Classic
    • J-Link PLUS Compact
    • J-Link BASE Classic
    • J-Link BASE Compact
    • Flasher PRO
    • Flasher PRO XL
    • Flasher Compact
    • Flasher Portable PLUS
    • Flasher Secure
    • List of downloads
    • Pricing
    • Buy now
    • Regulatory documents

    Headquarters

    SEGGER Microcontroller GmbH

    Ecolab-Allee 5
    40789 Monheim am Rhein, Germany
    info@segger.com
    Tel.: +49-2173-99312-0
    Fax: +49-2173-99312-28

    Locations

    USA: SEGGER Microcontroller Systems LLC

    Boston area
    101 Suffolk Lane
    Gardner, MA 01440, USA
    us-east@segger.com
    Tel.: +1-978-874-0299
    Fax: +1-978-874-0599

    Silicon Valley
    Milpitas, CA 95035, USA
    us-west@segger.com
    Tel.: +1-408-767-4068

    China: SEGGER Microcontroller China Co., Ltd.

    Room 218, Block A, Dahongqiaoguoji
    No. 133 Xiulian Road
    Minhang District, Shanghai 201199, China
    china@segger.com
    Tel.: +86-133-619-907-60

    ISO 9001 certified

    ISO 9001

    30+ years of experience

    First-class embedded software tools since 1992
    • Imprint
    • Disclaimer
    • Code of Conduct
    • Privacy Policy
    © 2025 SEGGER - All rights reserved.