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SEGGER Evaluation Software for RISC-V Architecture

SEGGER - RTOS embOS Product Icon
SEGGER - compression tool emCompress Product Icon
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SEGGER - Filesystem emFile Product Icon
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SEGGER provides board support packages (BSPs) and complete projects, available for various Evaluation boards. Different software packages are available for different boards.

Some packages are executable demos which can not be modified; some packages are trial versions which come with the software in a library and the application in source code form, as well as a project for the IDE that has been used.

Trial versions can usually be recompiled easily in less than a minute if the required compiler and IDE is installed. The application program can be modified, allowing intensive tests of the software. emWin trial versions usually also contain a simulation environment which allows test and recompilation on a PC.

Below is a list of supported Evaluation boards. The software can easily be ported to other hardware platforms. If you are looking for software for an Evaluation board not in this list, please get in touch with us at

RISC-V Digilent ARTY

The Arty A7-35T FPGA Development Board is an FPGA board, that can host a bitstream to become a RISC-V processor. The below examples are based on the SiFive E31 bitstreams, that are available as a trial version from SiFive's web page.

RISC-V arty

SEGGER Evaluation Software

Included Components:

ProductSupported features


Core + Profiling

Other Downloads

Download   embOS trial with SystemView for RISC-V and SEGGER Embedded Studio

Download   Embedded Studio for RISC-V, Windows, 64-bit version

Download   Embedded Studio for RISC-V, Windows, 32-bit version

Download   Embedded Studio for RISC-V, macOS

Download   Embedded Studio for RISC-V, Linux, 64-bit version

Download   Embedded Studio for RISC-V, Linux, 32-bit version

Download   Embedded Studio for RISC-V

SEGGER Notifications

   to SEGGER Evaluation Software Notifications

Data Sheets

Digilent ARTY

  • Xilinx Artix-7 XC7A35T-L1CSG324I FPGA
  • On-chip analog-to-digital converter
  • Programmable over JTAG and quad-SPI flash
  • 256MB DDR3L with a 16-bit bus @ 667MHz
  • 16MB quad-SPI flash
  • 10/100 Mb/s Ethernet
  • USB-UART bridge
  • Four interfaces (32 I/O)

Xilinx Artix-35T FPGA

  • 33,280 logic cells in 5200 slices (each slice contains four 6-input LUTs and 8 flip-flops)
  • 1,800 Kbits of fast block RAM
  • Five clock management tiles, each with a phaselocked loop (PLL)
  • 90 DSP slices
  • Internal clock speeds exceeding 450MHz
  • On-chip analog-to-digital converter (XADC)
  • Programmable over JTAG and Quad-SPI Flash