emFile - NAND Flash Driver
- Fail-safe in case of unexpected reset
- Very high read and write performance
- Low RAM usage
- Trial hardware available with socket for NAND flash
- Block grouping facilitates use of large NAND flashes
Fail-safe device drivers that support SLC and MLC NAND flash and multi-bit ECC in software or hardware.
About the emFile NAND Drivers
The emFile NAND drivers allow the file system layer to efficiently write and read blocks of data (logical sectors) to and from a NAND flash device. All the details regarding the access to NAND flash such us the identification of the NAND flash device, erasing of NAND physical blocks, writing the data page-wise, etc. are managed internally by the NAND drivers. The NAND flash device is presented to the upper file system layer as an array of logical sectors that are identified by a 0-based logical sector index.
emFile comes with two drivers for NAND flash devices:
Works with SLC (Single-Level Cell) NAND flash devices which require 1-bit error correction. It also comes with support for the Adesto (Atmel) DataFlash devices.
The NAND drivers are fail-safe. This means that the drivers make only atomic actions and take the responsibility that the data managed by the file system is always valid. In case of a power loss or a power reset during a write operation, it is always assured that only valid data is stored in the flash. If the power loss interrupts the write operation, the old data will be kept and the block not corrupted.
Both NAND drivers come with support for active and passive wear leveling. The purpose of the wear leveling is to extend the lifetime of the NAND flash device by making sure that the NAND blocks are evenly erased. This is realized by keeping track of the lowest erase count and of the index of the NAND block erased last. When an erased block is required the NAND driver searches for the next available NAND block in the row and it checks the difference between the erase count of the found NAND block and the lowest erase count. If the difference is larger than a specified maximum than the NAND block with the lowest erase count is used instead to store data. This procedure guarantees that the NAND blocks which store constant data are also erased.
Bad Block Management
Blocks can go defective during the lifetime of a NAND flash which makes necessary to identify them as such. The bad block management help the NAND drivers identify and mark blocks as defective. Blocks marked as defective at manufacturing time or by the NAND driver are not used for data storage. A block is recognized as defective when the first byte in the spare area of the first or second page of that block is different than 0xFF. The driver marks a block as defective in the following cases:
- When the NAND flash device reports an error after a write operation.
- When the NAND flash device reports an error after an erase operation.
- When an uncorrectable bit error is detected via ECC on the data read from NAND flash device.
The NAND drivers perform the garbage collection automatically during the write operations. If no empty blocks are available to store the data, new empty ones are created by erasing blocks that contain invalid data. The garbage collection operation can potentially reduce the write throughput of an application since the block erase operation takes a relatively long time to complete. For applications which require maximum write throughput, the NAND drivers provide the possibility to perform the garbage collection in the application for example when the file system is idle.
Block grouping is a feature that can be used to reduces the RAM memory ussage for block management and thus allows using large capacity NAND flash devices with smaller microcontrollers. With this feature enable the NAND drivers treat multiple consecutive blocks as a single block to considerably reduce the memory used for administrating the NAND flash memory. The size of a block group is scalable according to the requirements of the application.
How Devices Operate
A NAND flash is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for command inputs. NAND flash devices consist of a number of blocks. Every block contains a number of pages, typically 64. The pages can be written to individually, one at a time. When writing to a page, bits can only be changed from 1 to 0. Only entire blocks (all pages in the block) can be erased at a time. Erasing means bringing all memory bits in all the pages of the block to logical 1.
Small NAND flash devices (up to 256 Mbytes) have a page size of 528 bytes that is 512 for user data and 16 spare bytes for storing management information (ECC, block index, etc.) related the user data in the page. Large NAND devices (256 Mbytes or more) typically have a page size of 2112 bytes: 2048 bytes for user data and 64 bytes for management information.
The NAND drivers can handle any common page and block size, as well as logical sector sizes smaller than page size. This allows using a file system with a logical sector size of either 512, 1024 or 2048 bytes per sector on a NAND flash with 2 Kbyte pages.
For example, a typical NAND flash with a size of 256 MBytes has 2048 blocks of 64 pages of 2112 bytes (2048 bytes for data + 64 bytes spare area).
DataFlash devices work in a similar way to NAND flash devices but they have capacities of only a few mega bytes.
Pin description of NAND flash
|CE||Chip Enable||The CE input enables the device. Signal is active low. If the signal is inactive, device is in standby mode.|
|WE||Write Enable||The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.|
|RE||Read Enable||The RE input is the serial data-out control. When active (low) the device outputs data.|
|CLE||Command Latch Enable||This pin should be low, when writing commands to the command register.|
|ALE||Address Latch Enable||When active, an address can be written.|
|WP||Write Protect||Typically connected to VCC (recommended), but may also be connected to port pin.|
|R/B||Ready/Busy Output||The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or read operation is in process. It returns to high state when the operation is completed. It is an open drain output. Should be connected to a port pin with pull-up. If available a port pin which can trigger an interrupt should be used.|
|I/O0 - I/O7||Data Inputs/Outputs||The I/O pins are used to input command, address and data, and to output data during read operations.|
|I/O8 - I/O15||Data Inputs/Outputs||I/O8 - I/O15 16-bit flashes only.|
Pin Description of DataFlash
|CS||Chip Select|| |
This pin selects the DataFlash device. The device is selected, when CS pin is driven low.
|SCLK||Serial Clock|| |
The SCLK pin is an input-only pin and is used to control the flow of data to and from the DataFlash. Data is always clocked into the device on the rising edge of SCLK and clocked out of the device on the falling edge of SCLK.
|SI||Serial Data In|| |
The SI pin is an input-only pin and is used to transfer data into the device. The SI pin is used for all data input including opcodes and address sequences.
|SO||Serial Data Out|| |
This SO pin is an output pin and is used to transfer data serially out of the device.
- Data transfer width is 8 bit.
- Chip Select (CS) sets the card active at low-level and inactive at high level.
- Clock signal must be generated by the target system. The serial flash chips are always in slave mode.
- Bit order requires most significant bit (MSB) to be sent out first.
DataFlash devices are commonly used when low pin count and easy data transfer are required.