RISC-V is an open-source core and instruction set. It provides comparable performance and efficiency to popular architectures like ARM and also allows to extend the instruction set by custom instructions which can provide increased performance for special use-cases.
J-Link supports the following RISC-V architectures:
- RISC-V 32-bit (RV32)
- RISC-V 64-bit (RV64)
Supported debug architectures
J-Link supports the following RISC-V debug architectures:
- Official RISC-V debug spec. 0.11
- Official RISC-V debug spec. 0.13
- RISC-V behind a DAP
RISC-V behind a DAP
While the official RISC-V debug spec. specifies RISC-V for JTAG only, to be accessed via specific JTAG instructions, this spec. may not be applicable for hybrid setups where there are for example ARM cores in parallel to the RISC-V ones on the same device. For these setups it makes sense to have the RISC-V cores located behind a CoreSight DAP which allows to access all ARM cores and RISC-V cores through the same debug signals and the same debug header on a hardware.
J-Link supports this type of setup
The same J-Link software package as for all other supported cores and architectures is also used for RISC-V. No separate package etc. is required.
Supported debuggers and IDEs
The following debuggers and IDEs are supported by J-Link for RISC-V:
- SEGGER Ozone
- SiFive FreedomStudio
- Vanilla Eclipse with GDB
For a detailed list of supported devices, please click here.
Supported debug interfaces
J-Link supports the following debug interfaces for RISC-V:
- JTAG (IEEE 1149.1)
- cJTAG (IEEE 1149.7)
- SWD (for RISC-V behind a DAP setups only)
Are unlimited breakpoints in flash memory available?
A: Yes, the J-Link feature "unlimited breakpoints when debugging in flash memory" is supported for RISC-V.
Does J-Link also support custom RISC-V cores?
A: Yes, as long as the core provides one of the supported debug architectures listed on this page.