emFile - SLC1 NAND Flash Driver
NAND driver designed to support one or multiple SLC (Single-Level Cell) NAND flashes which require 1-bit ECC.
About the Driver
The SLC1 NAND driver enables the file system to access raw SLC NAND flash and DataFlash devices. It provides a very high performance with a reduced RAM and ROM usage. The data reliability is ensured by making use of 1-bit ECC. The SLC1 NAND driver makes efficient use of the storage by mapping more than one logical sector to a physical page of the device. Small and large block NAND flash devices are supported which gives the user more choices in selecting a storage device.
In general, the driver supports almost all Single-Level Cell NAND flashes (SLC). This includes NAND flashes with page sizes of 512+16 and 2048+64 bytes. The table below shows the NAND flash devices that have been tested or are compatible with a tested device.
Parallel NAND Flash and Serial DataFlash Devices
|Device Type||Page Size [Bytes]||Storage Capacity [Bits]|
Support for Devices Not Available in the List
Most other NAND flash devices are compatible with one of the supported devices. Thus the driver can be used with these devices or may only need a little modification, which can be easily done. Get in touch with us, if you have questions about support for devices not in this list.
Performance and Resource Usage
The SLC1 NAND driver has been carefully designed to make effective use of RAM. The amount of RAM required by the driver depends on the runtime configuration and on the connected NAND flash device. In a typical embedded system which uses a 2 Gbit NAND flash, the driver requires less than 6 KBytes of RAM.
The SLC1 NAND driver has a very high read and write performance. For example, on an ARM7 CPU running at 48 MHz, the driver reaches a transfer speed of 3.8 MBytes/sec for writing and 5.9 MBytes/sec for reading. This makes the driver one of the fastest implementations on the market!
Theory of Operation
NAND flash devices are divided into physical blocks and physical pages. One physical block is the smallest erasable unit; one physical page is the smallest writable unit. Each physical block consists of multiple physical pages. On small block NAND flash devices one physical block contains typically 16, 32 or 64 pages and every physical page has a size of 528 bytes (512 data bytes + 16 spare bytes). Large block NAND flash devices contain blocks made up of 64 pages, each page containing 2112 bytes (2048 data bytes + 64 spare bytes).
The SLC1 NAND driver uses the spare bytes for the following purposes:
- To check if the data status byte and block status are valid. If they are valid the driver uses this sector. When the driver detects a bad sector, the whole block is marked as invalid and its content is copied to a non-defective block.
- To store/read an ECC (Error Correction Code) for data reliability. When reading a sector, the driver also reads the ECC stored in the spare area of the sector, calculates the ECC based on the read data and compares the ECCs. If the ECCs are not identical, the driver tries to recover the data, based on the read ECC. When writing to a page the ECC is calculated based on the data the driver has to write to the page. The calculated ECC is then stored in the spare area.
Error Correction Code (ECC)
The SLC1 NAND driver is highly speed optimized and offers a better error detection and correction than a standard memory controller ECC. The ECC is capable to correct a single bit error and to detect a 2-bit error. When a block for which the ECC is computed has 2 or more bit errors, the data cannot be corrected. Standard memory controllers compute an ECC for the complete blocksize (512 / 2048 bytes). The SLC1 NAND driver computes the ECC for data chunks of 256 bytes (e.g. a page with 2048 bytes is divided into 8 parts of 256 bytes), so the probability to detect and also correct data errors is much higher. This enhancement is realized with a very good performance. The ECC computation of the SLC1 NAND driver is highly optimized, so that a performance of about 18 Mbytes/second can be achieved on a ATM7 CPU running at 48 MHz.
We suggest the use of the the SLC1 NAND driver without the usage of a memory controller, because the performance of the driver is very high and the error correction is much better if it is controlled from driver side.