Flash Translation Layer for NAND Flash
- SLC, MLC NAND Flash, and DataFlash support
- ECC and fail-safe operation
- Minimal RAM and ROM usage with high performance
Key features
Broad flash support
Supports modern SLC and MLC NAND flash devices using parallel or serial interfaces as well as DataFlash devices.
Active and passive wear leveling
Distributes erase cycles across the NAND flash to extend device lifetime. Passive wear leveling also includes blocks containing static data.
Error correction
Detects and corrects single and multiple bit errors in user and management data using hardware ECC or software routines such as emLib ECC.
Bad-block management
Automatically detects and excludes defective blocks from data storage, including factory-marked blocks and blocks that become defective during operation.
Fail-safe operation
Uses atomic operations to maintain valid data in case of an unexpected power loss or reset. If a write operation is interrupted, the previously valid data is retained.
Low memory footprint
Optimized for resource-constrained embedded systems, requiring less than 8 KB of RAM in a typical system using a 2 GBit NAND flash device.
Supported devices
In general, the Flash Translation Layer supports almost all popular Single-Level Cell NAND flashes (SLC) with a page size larger than 2048+64 bytes. The table below shows the NAND flash devices that have been tested or are compatible with a tested device:
How the Flash Translation Layer works
NAND flash organization
NAND flash devices consist of physical blocks and pages. A block is the smallest erasable unit, while a page is the smallest writable unit. Pages can be written individually, with bits changing from 1 to 0. Erasing is performed at block level and resets all bits within the block to logical 1.
Small NAND flash devices with capacities up to 256 MB typically have a page size of 528 bytes, consisting of 512 bytes for user data and 16 spare bytes for management information. Larger NAND flash devices typically use pages of 2112 bytes, consisting of 2048 bytes for user data and 64 spare bytes.
The Flash Translation Layer can handle common page and block sizes as well as logical sector sizes smaller than the physical page size. This allows emFile to use logical sectors of 512, 1024, or 2048 bytes, for example, on NAND flash with 2 KB pages.
DataFlash
The Flash Translation Layer also supports DataFlash devices. DataFlash operates in a similar way to NAND flash but typically offers capacities of only a few megabytes. It is commonly used when a low pin count and simple data transfer are required.
DataFlash uses an SPI interface for the data transfer with the data being exchanged 8 bits at a time. The most significant bit (MSB) is transferred first.
Management data and spare area
The Flash Translation Layer uses the spare area of NAND flash pages to store information required for reliable flash management. This includes:
- Information about whether a block is valid or defective
- Mapping information between physical pages and logical sectors
- Block erase counts for wear leveling
- Information about whether a page contains valid data
- Error Correction Codes (ECC) for data integrity
This information enables the Flash Translation Layer to manage the physical characteristics of NAND flash transparently for the file system.
Data reliability and integrity
Error correction
NAND flash is subject to bit errors that can occur in both user data and management data. The Flash Translation Layer uses Error Correction Codes (ECC) to detect and correct these errors.
ECC can be calculated using dedicated hardware, such as ECC functionality integrated into the NAND flash device or memory controller, or entirely in software using routines such as those provided by emLib ECC.
When data is written, the corresponding ECC is calculated and stored in the spare area. During a read operation, the stored ECC is compared with the ECC calculated from the retrieved data. If an error is detected, the Flash Translation Layer attempts to correct the data using the stored ECC.
Data scrubbing
Data stored in NAND flash can degrade over time. To maintain data integrity, the Flash Translation Layer performs data scrubbing during read operations.
During scrubbing, the data is read and checked for errors. Correctable errors are repaired using ECC and the corrected data is written back to the flash, refreshing the stored information before degradation can result in an uncorrectable error.
The threshold that determines when data is scrubbed is configurable at runtime. This allows the application to balance data integrity against the additional flash wear caused by refreshing data.
NAND write management
To increase data reliability, the Flash Translation Layer performs only a single write operation to a NAND flash page between two block erase cycles.
Avoiding repeated partial-page programming reduces the risk of bit corruption and provides compatibility with modern SLC and MLC NAND flash devices.
Wear leveling
NAND flash blocks support only a limited number of erase cycles. The Flash Translation Layer therefore provides both active and passive wear leveling to distribute erase operations across the available flash blocks and extend the usable lifetime of the device.
The Flash Translation Layer tracks erase counts and selects blocks in a way that prevents individual blocks from being erased significantly more often than others. Blocks containing static data are also taken into account, ensuring that they do not remain permanently unused while other blocks accumulate erase cycles.
Flash management
Block grouping
Block grouping reduces the amount of RAM required for block management, enabling large-capacity NAND flash devices to be used with resource-constrained microcontrollers.
When block grouping is enabled, multiple consecutive physical blocks are managed as a single block group. This considerably reduces the amount of memory required to administer the NAND flash. The size of a block group can be configured according to the requirements of the application.
Garbage collection
The Flash Translation Layer performs garbage collection automatically to reclaim storage occupied by invalid data. If no empty blocks are available for new data, blocks containing invalid data are erased and made available for subsequent write operations.
Because block erase operations can temporarily reduce write throughput, garbage collection can also be performed while the file system is idle. This allows applications with high or time-critical write requirements to prepare free blocks before they are needed.
Performance and resource usage
The Flash Translation Layer is optimized for efficient use of RAM and ROM. Actual memory requirements depend on the runtime configuration and the connected NAND flash device.
In a typical embedded system using a 2 GBit NAND flash device, the Flash Translation Layer requires less than 8 KB of RAM.
High transfer speeds can be achieved even on microcontrollers. For example, on a Cortex-M CPU running at 168 MHz, the Flash Translation Layer reaches transfer speeds of up to:
- 4.6 MB/s for writing
- 8.0 MB/s for reading
Actual performance depends on the target hardware, NAND flash device, interface, and system configuration.
Custom hardware support
The Flash Translation Layer can be adapted to custom hardware configurations.
When GPIO pins or a simple memory controller are used to access the NAND flash, typically only the hardware layer needs to be ported. Changes to the physical layer are normally not required.
When using a specialized memory controller, such as a custom FPGA implementation, the physical layer can be adapted to the controller. In this case, a separate hardware layer may not be required because the memory controller handles the hardware access.
Interface reference
Pin description of NAND flash
| Pin | Meaning | Description |
|---|---|---|
| CE | Chip Enable | The CE input enables the device. Signal is active low. If the signal is inactive, device is in standby mode. |
| WE | Write Enable | The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse. |
| RE | Read Enable | The RE input is the serial data-out control. When active (low) the device outputs data. |
| CLE | Command Latch Enable | This pin should be low, when writing commands to the command register. |
| ALE | Address Latch Enable | When active, an address can be written. |
| WP | Write Protect | Typically connected to VCC (recommended), but may also be connected to port pin. |
| R/B | Ready/Busy Output | The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or read operation is in process. It returns to high state when the operation is completed. It is an open drain output. Should be connected to a port pin with pull-up. If available a port pin which can trigger an interrupt should be used. |
| I/O0 - I/O7 | Data Inputs/Outputs | The I/O pins are used to input command, address and data, and to output data during read operations. |
| I/O8 - I/O15 | Data Inputs/Outputs | I/O8 - I/O15 16-bit flashes only. |
Pin Description of DataFlash
| Pin | Meaning | Description |
|---|---|---|
| CS | Chip Select | This pin selects the DataFlash device. The device is selected, when CS pin is driven low. |
| SCLK | Serial Clock | The SCLK pin is an input-only pin and is used to control the flow of data to and from the DataFlash. Data is always clocked into the device on the rising edge of SCLK and clocked out of the device on the falling edge of SCLK. |
| SI | Serial Data In | The SI pin is an input-only pin and is used to transfer data into the device. The SI pin is used for all data input including opcodes and address sequences. |
| SO | Serial Data Out | This SO pin is an output pin and is used to transfer data serially out of the device. |