J-Link LITE Debug Probe for ARM7/9 and Cortex Cores
Debug probe for ARM7/9 and Cortex cores. J-Link LITE is a fully functional version of SEGGER J-Link.
- Very small form factor
- Fully software compatible to J-Link
- Supported CPUs: ARM7/9/11, Cortex-A5/A8/A9, Cortex-M0/M1/M3/M4/M7, Cortex-R4/R5
- JTAG clock up to 2 MHzSWD, SWO supported for Cortex-M devices
- Flash download into supported MCUs
- Standard .1" 20-pin male JTAG/SWD connector (compatible with J-Link)
- 3.3V target interface voltage
About J-Link LITE
J-Link LITE is a fully functional version of SEGGER J-Link. If you are selling evaluation-boards, J-Link Lite is an inexpensive debug probe solution for you. Your customer receives a widely acknowledged JTAG debug probe which allows him to start right away with his development.
Specifications
| Specification | Value | ||||
|---|---|---|---|---|---|
| Supported OS | Microsoft Windows 2000 Microsoft Windows XP Microsoft Windows XP x64 Microsoft Windows 2003 Microsoft Windows 2003 x64 Microsoft Windows Vista Microsoft Windows Vista x64 Microsoft Windows 7 Microsoft Windows 7 x64 Microsoft Windows 8 Microsoft Windows 8 x64 Microsoft Windows 10 Microsoft Windows 10 x64 Linux macOS 10.5 and higher | ||||
| Electromagnetic compatibility (EMC) | EN 55022, EN 55024 | ||||
| Operating temperature | +5°C ... +60°C | ||||
| Storage temperature | -20°C ... +65 °C | ||||
| Relative humidity (non-condensing) | Max. 90% rH | ||||
| Size (without cables) | 28mm x 26mm x 7mm | ||||
| Weight (without cables) | 6g | ||||
| Mechanical | |||||
| USB interface | USB2.0 (Full-Speed), Mini USB | ||||
| Target interface | JTAG 20-pin (14-pin adapter available) | ||||
| JTAG/SWD Interface, Electrical | |||||
| Power supply | USB powered Max. 50mA + Target Supply current. | ||||
| Target interface voltage (VIF) | 3.3V | ||||
| Target supply voltage | 4.5V ... 5V (if powered with 5V on USB) | ||||
| Target supply current | Max. 300mA | ||||
| LOW level input voltage (VIL) | Max. 40% of VIF | ||||
| HIGH level input voltage (VIH) | Min. 60% of VIF | ||||
| JTAG/SWD Interface, Timing | |||||
| Data input rise time (Trdi) | Max. 20ns | ||||
| Data input fall time (Tfdi) | Max. 20ns | ||||
| Data output rise time (Trdo) | Max. 10ns | ||||
| Data output fall time (Tfdo) | Max. 10ns | ||||
| Clock rise time (Trc) | Max. 10ns | ||||
| Clock fall time (Tfc) | Max. 10ns | ||||
Licensing
J-Link Lite is only delivered and supported as part of a starter kit, which includes an evaluation board. It is not sold separately. It may only be used with the evaluation board it came with. Support is given via the eval board manufacturer and via SEGGER forum.
If you are interested in J-Link LITE, please contact info@segger.com.
Package Content
J-Link LITE
.1" 20-pin ribbon cable
Mini-USB cable