SEGGER and Codasip announce cooperation on RISC-V
SEGGER’s J-Link debug probe supports RISC-V debug on Codasip’s processor cores. Furthermore, J-Link, using the Open Flashloader concept, allows programming of flash memories connected to devices using Codasip RISC-V cores, while Embedded Studio’s Linker and Runtime Libraries are perfect for minimizing code size.
“Having SEGGER’s J-Link and Embedded Studio fully support our RISC-V cores represents excellent added value for our ecosystem,” says Roddy Urquhart, Sr. Marketing Director at Codasip.
"As a member of the RISC-V foundation, we are excited to further contribute to the ecosystem by supporting Codasip,” says Ivo Geilenbruegge, Managing Director of SEGGER. "SEGGER is highly engaged in the RISC-V market and started offering software libraries and tools early on. We are excited to continue our collaboration with Codasip."
Codasip's family of 32-bit embedded processors (names beginning with "L") and 64-bit embedded processors (names beginning with "H") are based on the RISC-V Instruction Set Architecture (ISA) and can be customized to meet domain-specific requirements.
Codasip delivers leading-edge RISC-V processor IP and high-level processor design tools, providing IC designers with all the advantages of the RISC-V open ISA, along with the unique ability to customize the processor IP. As a founding member of RISC-V International and a long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded and application processors. Formed in 2014 and headquartered in Munich, Germany, Codasip currently has R&D centers in Europe and sales representatives worldwide.
For more information about our products and services, visit www.codasip.com.
For more information about RISC-V, visit www.riscv.org.