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Cortex-M, IAR

embOS-MPU for Cortex-M was developed for and with IAR EWARM. It comes with various easy to use start projects for IAR EWARM. Initialization code for different Cortex-M starter boards is included. Software development with JTAG tools like J-Link is possible.


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Resources and performance data

Memory usage
Kernel size (ROM) Approx. 2300 bytes
Kernel RAM usage 95 bytes
RAM usage per task control block 244 bytes
RAM usage per resource semaphore 16 bytes
RAM usage per counting semaphore 8 bytes
RAM usage per mailbox 24 bytes
RAM usage per software timer 20 bytes
RAM usage event 0 bytes
Min. stack-size per task (RAM) 80 bytes
Context switch time 3.4 µs
Interrupt latency time Zero
Kernel CPU usage/TICK Less than .2% of total calculation time at 1000 interrupts/second (1ms TICK)
Basic time unit (TICK) Typ. 1 ms, min. 20 µs (50 kHz interrupt frequency)
Max. no. of privileged tasks Unlimited (by available RAM only)
Max. no. of unprivileged tasks Unlimited (by available RAM only)
Max. no. of mailboxes Unlimited (by available RAM only)
Max. no. of semaphores Unlimited (by available RAM only)
Max. no. of software timers Unlimited (by available RAM only)
Max. no. of priorities Unlimited
Stack size idle task (RAM) 0 (no memory needed)
Nested interrupts Permitted
Task switches from within ISR Possible

Absolute values given above were measured using an embOS-MPU XRelease build on an STM32F457 CPU running at 168MHz.

Board support packages

embOS-MPU comes with ready to go start projects and support packages for various Cortex-M CPUs and starterboards.

CPU Eval board
SiliconLabs EZR32LG330 SiliconLabs EZR32LG330 Leopard Gecko evalboard