embOS-Classic RISC-V IAR
embOS-Classic RTOS port for RISC-V was developed for and with IAR for RISC-V and can be used on any RISC-V device.
Board support packages (BSPs) for different RISC-V devices and evaluation boards are included.
Resources and performance data
| Memory usage | |
|---|---|
| Kernel ROM | Approx. 2000 Bytes |
| Kernel RAM | 110 Bytes |
| Task RAM: Task control block | 36 Bytes |
| Task RAM: Minimum stack size | 64 Bytes |
| Timing | |
| Context switching time | 180 Cycles (1.6 µs with GigaDevice GD32VF103 running at 108 MHz) |
| Interrupt latency time | Zero |
Board support packages
embOS-Classic for RISC-V and IAR may be used on any RISC-V device. The most recent release includes the following board support packages (BSPs), but further board support packages may easily be created based on this release.
Do you want us to create the BSP on your behalf? Please contact us.
| CPU | Evaluation board |
|---|---|
| GigaDevice GD32VF103 | GigaDevice GD32VF103V-Eval |
| SiFive E31 RISC-V Core IP FPGA Eval Kit | Digilent Artix-7 FPGA Dev Board |