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ISO 9001 certified


TLCS900, Toshiba

embOS for TLCS900 was developed for and with TOSHIBA's CC900 compiler and supports all memory models offered by this compiler.
The distribution contains an easy to use start workspace for TOSHIBA's Integrated Development Environment.

 

Pricing Trial download Notification Subscribe to embOS software notification Release Notes

 

Resources and performance data

Memory usage
Kernel size (ROM) Approx. 1600 bytes
Kernel RAM usage 41 bytes
RAM usage per task control block 28 bytes
RAM usage per resource semaphore 6 bytes
RAM usage per counting semaphore 2 bytes
RAM usage per mailbox 14 bytes
RAM usage per software timer 14 bytes
RAM usage event 0 bytes
Min. stack-size per task (RAM) 100 bytes
Timing
Context switch time 296 clock cycles (14.8 µs), independent of number of tasks
Interrupt latency time for high priority interrupt Max. 20 clock cycles (1.0 µs)
Kernel CPU usage/TICK Less than .2% of total calculation time at 1000 interrupts/second (1ms TICK)
Basic time unit (TICK) Typ. 1 ms, min. 10 µs (100 kHz interrupt frequency)
Features
Max. no. of tasks Unlimited (by available RAM only)
Max. no. of mailboxes Unlimited (by available RAM only)
Max. no. of semaphores Unlimited (by available RAM only)
Max. no. of software timers Unlimited (by available RAM only)
Max. no. of priorities 255
Stack size idle task (RAM) 0 (no memory needed)
Nested interrupts Permitted
Task switches from within ISR Possible

Absolute data given above were measured with embOS release build on a TMP94F53 CPU running at 20MHz in __cdecl memory model.

 

Board support packages

embOS comes with lots of ready to go start projects and support packages for various CPUs and starterboards.

CPU Eval board
Toshiba H900H2 Toshiba H900H2 evalboard