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ISO 9001 certified


Cortex-M, TICC

embOS for Cortex M was developed for and with TICC and supports all memory models offered by these compiler. It comes with easy to use start projects. Initilization code for different Cortex M starter boards is included. Software development with with JTAG tools like J-Link is possible.

 

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Resources and performance data

Memory usage
Kernel size (ROM) Approx. 1700 bytes
Kernel RAM usage 71 bytes
RAM usage per task control block 32 bytes
RAM usage per resource semaphore 16 bytes
RAM usage per counting semaphore 8 bytes
RAM usage per mailbox 24 bytes
RAM usage per software timer 20 bytes
RAM usage event 0 bytes
Min. stack-size per task (RAM) 80 bytes
Timing
Context switch time 4.1 µs
Interrupt latency time Zero
Kernel CPU usage/TICK Less than .2% of total calculation time at 1000 interrupts/second (1ms TICK)
Basic time unit (TICK) Typ. 1 ms, min. 20 µs (50 kHz interrupt frequency)
Features
Max. no. of tasks Unlimited (by available RAM only)
Max. no. of mailboxes Unlimited (by available RAM only)
Max. no. of semaphores Unlimited (by available RAM only)
Max. no. of software timers Unlimited (by available RAM only)
Max. no. of priorities Unlimited
Stack size idle task (RAM) 0 (no memory needed)
Nested interrupts Permitted
Task switches from within ISR Possible

Absolute values given above were measured with embOS XRelease build on an TI TM4C129 CPU running at 120MHz.

Board support packages

embOS comes with lots of ready to go start projects and support packages for various Cortex M CPUs and starterboards.

CPU Eval board
TI TM4C129 TI TM4C129 development kit
TI MSP432P401R MSP432P401R LaunchPad development kit