What's Happening at SEGGER?

2021 |
Nov. 10
RISC-V, embOS, Press Releases, Press Releases 2021

SEGGER's embOS-Ultra now available for RISC-V

SEGGER’s embOS-Ultra, a revolutionary new RTOS using Cycle-resolution Timing, is now available for RISC-V processors.

Cycle-resolution Timing eliminates the periodic tick interrupt, reducing CPU load and energy use. Scheduling of all time-based events such as timeouts, delays, and periodic timers, can now be specified in microseconds or CPU cycles. Cycle- resolution Timing technology replaces target-specific techniques for precise timing with clean and consistent API calls.

"We have made our new embOS-Ultra available for RISC-V as part of our continued support for the ever-growing RISC-V community,” says Ivo Geilenbruegge, Managing Director of SEGGER. “As a strategic member of the RISC-V Foundation, we have optimized our software and development tools for the industry at a very early stage. We remain committed to adapting our products to the evolving RISC-V market, keeping them truly future- proof.”

Upgrading to embOS-Ultra from embOS simply works as it maintains full API compatibility with classic embOS. At the same time, it provides CPU-cycle precision for scheduling through additional API calls. No application changes are required as the existing API and RTOS behavior is maintained. The traditional embOS API can be used together with the extended high-precision embOS-Ultra API in the same application; there is no need to choose one or the other.

Applications can instantly benefit from the upgrade to embOS-Ultra, saving energy due to the elimination of the periodic tick and the ability to schedule in microseconds or even CPU cycles.

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