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📄 SEGGER Assembler User Guide & Reference Manual

SEGGER Assembler User Guide & Reference Manual

An assembler for Arm microcontrollers.

About the assembler

Introduction

This section presents an overview of the SEGGER Assembler and its capabilities.

What is the SEGGER Assembler?

The SEGGER Assembler is a fast assembler that processes Cortex-M assembly language source files. It is designed to be very flexible, yet simple to use.

The assembler accepts GNU, Arm, and IAR syntax source files and will assemble them to Arm ELF object files that can be linked by a standard Cortex-M linker.

Assembler features

The SEGGER Assembler has the following features:

Command-line options

Command line option naming is generally compatible with the following toolsets:

Input file options

--auto-import

Summary

Automatically import symbols.

Syntax

--auto-import

Description

This option instructs the assembler to automatically define as symbol as an external (imported) symbol if it is used and has not been declared with a different storage class.

See also

--no-auto-import

--no-auto-import

Summary

Do not automatically import symbols.

Syntax

--no-auto-import

Description

This option instructs the assembler not to automatically define as symbol as an external (imported) symbol and to require that all symbols are declared as local or external before their first use.

See also

--auto-import

--define

Summary

Define symbol.

Syntax

--define symbol=value
-Dsymbol=value

Description

This option defines the symbol symbol to the numeric value value.

--dependency-file

Summary

Write dependencies to file.

Syntax

--dependency-file filename
--MD filename

Description

This option instructs the assembler to write the list of dependencies (included source files and included binary files) to the fle filename.

--include

Summary

Add include directory.

Syntax

--include path
-Ipath

Description

This option adds the path path to the end of the list of directories to search for included source files and included binary files.

--input-syntax

Summary

Set source file syntax.

Syntax

--input-syntax=name
-fsyntax=name

Description

This option selects the source file syntax. The syntaxes accepted by the assembler are:

There is one additional syntax identifier:

The default is auto syntax where the assembler automatically determines the appropriate source file syntax using heuristics.

--via

Synopsis

Read additional options and input files from file.

Syntax

--via filename
--via=filename
-f filename
@filename

Description

This option reads the file filename for additional options and input files. Options are separated by spaces or newlines, and file names which contain special characters, such as spaces, must be enclosed in double quotation marks.

Notes

This option can only be provided on the command line and cannot appear in an indirect file.

Output file options

--keep-empty-sections

Summary

Keep empty sections in object file.

Syntax

--keep-empty-sections

Description

This option instructs the assembler to emit empty sections that have been created during assembly. An empty section is a section that is created using a section directive but has no instructions or data allocated to it.

The default is to eliminate empty sections.

See also

--no-keep-empty-sections

--no-keep-empty-sections

Summary

Eliminate empty sections from object file.

Syntax

--no-keep-empty-sections

Description

This option instructs the assembler to eliminate empty sections that have been created during assembly. An empty section is a section that is created using a section directive but has no instructions or data allocated to it.

The default is to eliminate empty sections.

See also

--keep-empty-sections

--keep-local-symbols

Summary

Keep local symbol definitions in object file.

Syntax

--keep-local-symbols

Description

This option instructs the assembler to include local symbol definitions created during assembly in the object file’s symbol table. Local symbols can be either an equate or a local label definition that is not exported as a global symbol.

The default is eliminate local symbols.

Note

Local symbols that start “.L” are never emitted to the object even with --keep-local-symbols in effect.

See also

--no-keep-local-symbols

--no-keep-local-symbols

Summary

Do not keep local symbol definitions in object file.

Syntax

--no-keep-local-symbols

Description

This option instructs the assembler to exclude local symbol definitions created during assembly from the object file’s symbol table. Local symbols can be either an equate or a local label definition that is not exported as a global symbol.

See also

--keep-local-symbols

--mapping-symbols

Summary

Include mapping symbols.

Syntax

--mapping-symbols

Description

This option includes mapping symbols in the Arm ELF file.

See also

--no-mapping-symbols

--no-mapping-symbols

Summary

Do not generate mapping symbols.

Syntax

--no-mapping-symbols

Description

This option produces an Arm ELF file that contains no code and data mapping symbols.

See also

--mapping-symbols

--output

Summary

Set output file name.

Syntax

--output filename
-o filename

--output=filename
-o=filename

Description

This option sets the Arm ELF output filename, typically with extension “o”.

--symbols

Summary

Include symbol table.

Syntax

--symbols

Description

This option includes the symbol table in the Arm ELF file. This does not automatically enable mapping symbol inclusion.

See also

--no-symbols

--no-symbols

Summary

Discard symbol table.

Syntax

--no-symbols

Description

This option eliminates all symbols from the Arm ELF file that are not required which includes the mapping symbols.

See also

--symbols

--pad-sections

Summary

Pad sections to alignment boundary.

Syntax

--pad-sections

Description

This option instructs the assembler to emit additional data to a section such that its size is a multiple of its alignment. Padding a section to a multiple of its alignment may waste space that a linker could otherwise utilize for section packing.

The default is not to pad sections.

See also

--no-pad-sections

--no-pad-sections

Summary

Do not pad sections to alignment boundary.

Syntax

--no-pad-sections

Description

This option instructs the assembler not to emit additional data to a section such that its size is a multiple of its alignment. Padding a section to a multiple of its alignment may waste space that a linker could otherwise utilize for section packing.

The default is not to pad sections.

See also

--pad-sections

Target selection options

--cpu=name

Summary

Set target core or architecture.

Syntax

--cpu=name
-cpu=name
-mcpu=name

Description

This option selects the target processor for the application and controls the construction of appropriate veneers when required.

The core names accepted are:

The architecture names accepted are:

The default is --cpu=cortex-m0.

-marm

Summary

Select Arm instruction set.

Syntax

-marm

Description

This option sets the default assembler instruction set to Arm (A32). The default instruction set is the instruction set if the source file does not select a specific instruction set using assembler source directives.

See also

-mthumb

-mbig-endian

Summary

Select big-endian byte order.

Syntax

-mbig-endian
-EB

Description

This option selects big-endian byte ordering for data and instructions.

The default is little-endian byte ordering.

See also

-mlittle-endian

-mlittle-endian

Summary

Select little-endian byte order.

Syntax

-mlittle-endian
-EL

Description

This option selects little-endian byte ordering for data and instructions.

The default is little-endian byte ordering.

See also

-mbig-endian

-mthumb

Summary

Select Thumb instruction set.

Syntax

-mthumb

Description

This option sets the default assembler instruction set to Thumb (T32). The default instruction set is the instruction set if the source file does not select a specific instruction set using assembler source directives.

See also

-marm

List file options

--list-diagnostics

Summary

Print diagnostics to listing.

Syntax

--list-diagnostics

Description

This option instructs the assembler to print all diagnostics at the end of the listing.

See also

--no-list-diagnostics

--no-list-diagnostics

Summary

Do not print diagnostics to listing.

Syntax

--no-list-diagnostics

Description

This option instructs the assembler not to print diagnostics at the end of the listing.

See also

--list-diagnostics

--list-file

Summary

Generate an assembler listing file.

Syntax

--list-file filename
--list-file=filename
-Lfilename

Description

Generates an assembler listing to the given filename.

--list-form-feed

Summary

Issue form feed between pages.

Syntax

--list-form-feed

Description

This option instructs the assembler to write a form feed between listing pages.

See also

--list-page-length, --no-list-form-feed

--no-list-form-feed

Summary

Do not issue form feed between pages.

Syntax

--no-list-form-feed

Description

This option ibhibits the assembler writing a form feed between listing pages.

See also

--list-form-feed

--list-html

Summary

Format listing as an HTML document.

Syntax

--list-html

Description

This option instructs the assembler to format the assembler listing as an HTML document. In this mode, listing pagination controls are ignored.

See also

--list-text

--list-page-length

Summary

Set number of lines per page.

Syntax

--list-page-length=value

Description

This option sets the number of lines per page to value. If value is zero, which is the default, the listing is not divided into pages.

See also

--list-form-feed

--list-symbols

Summary

Print symbol table to listing.

Syntax

--list-symbols

Description

This option instructs the assembler to print a symbol table at the end of the listing.

See also

--no-list-symbols

--no-list-symbols

Summary

Do not print symbol table to listing.

Syntax

--no-list-symbols

Description

This option instructs the assembler not to print a symbol table at the end of the listing.

See also

--list-symbols

--list-text

Summary

Format listing as a text document.

Syntax

--list-text

Description

This option instructs the assembler to format the assembler listing as an HTML document. In this mode, listing pagination controls are effective.

This is the default.

See also

--list-html

Control options

--remarks

Summary

Issue remarks.

Syntax

--remarks

Description

This option instructs the assembler to issue remarks for potential issues during assembly. This is the default.

See also

--no-remarks, --remarks-are-warnings, --remarks-are-errors

--remarks-are-errors

Summary

Elevate remarks to errors.

Syntax

--remarks-are-errors

Description

This option elevates all remark diagnostics issued by the assembler to errors.

See also

--no-remarks, --remarks, , --remarks-are-warnings

--remarks-are-warnings

Summary

Elevate remarks to warnings.

Syntax

--remarks-are-warnings
--remarks_are_warnings

Description

This option elevates all remark diagnostics issued by the assembler to warnings.

See also

--no-remarks, --remarks, , --remarks-are-errors

--no-remarks

Summary

Suppress remarks.

Syntax

--no-remarks

Description

This option disables all remark diagnostics issued by the assembler. Although remarks are suppressed, the total number of remarks that are suppressed by the assembler is shown at the end of linking:

C:> segger-as --via=app.ind
Copyright (c) 2017-2018 SEGGER Microcontroller GmbH    www.segger.com
SEGGER Assembler 2.10 compiled Apr 11 2018 10:50:34

Assembly complete: 0 errors, 0 warnings, 2 remarks suppressed

C:> _

See also

--remarks-are-warnings, --remarks-are-errors

--silent

Summary

Do not show output.

Syntax

--silent
-q

Description

This option inhibits all assembler status messages; only diagnostic messages are shown.

See also

--verbose

--verbose

Summary

Increase verbosity.

Syntax

--verbose
-v

Description

This option increase the verbosity of the assembler by one level.

See also

--silent

--warnings

Summary

Issue warnings.

Syntax

--warnings

Description

This option instructs the assembler to issue warnings for dubious use or inputs. This is the default.

See also

--no-warnings, --warnings-are-errors

--warnings-are-errors

Summary

Elevate warnings to errors.

Syntax

--warnings-are-errors
--fatal-warnings

Description

This option elevates all warning diagnostics issued by the assembler to errors.

See also

--no-warnings, --warnings

--no-warnings

Summary

Suppress warnings.

Syntax

--no-warnings

Description

This option disables all warning diagnostics issued by the assembler. Although warnings are suppressed, the total number of warnings that are suppressed by the assembler is shown at the end of linking:

C:> segger-as --via=app.ind
SEGGER Macro Assembler V2.10 compiled Jul  9 2020 14:30:42
Copyright (c) 2018-2020 SEGGER Microcontroller GmbH    www.segger.com

Assembly complete: 0 errors, 1 warnings suppressed, 0 remarks

C:> _

See also

--warnings, --warnings-are-errors

Expressions

GNU IAR ARM
(), prefix +, -, !, ~ (), prefix +, -, !, ~, LOW, HIGH, BYTE1, BYTE2, BYTE3, BYTE4, LWRD, HWRD, DATE, SFB, SFE, SIZEOF (), prefix +, -, :NOT:, :LNOT:
*, /, %, <<, >> *, /, % *, /, %, :MOD:
|, &, ^, ! +, - <<, >>, :SHL:, :SHR:, :ROL:, :ROR:
+, -, =, <>, , <, >, , <<, >> +, -, &, ^, :AND:, :OR:, :EOR:
&&, || &&, & =, <>, , /=, <, >, ,
||, |, ^, XOR &&, ||, :LAND:, :LOR:, :LEOR:
=, =, <>, , <, >, , , UGT, ULT

GNU syntax

Source file directives

.INCBIN

Include binary file.

Syntax

.INCBIN filename

Description

Searches for the binary file filename using include paths. Inserts the binary file into the current section as data with alignment 1.

Mode directives

.ARM

Select Arm instruction set.

Syntax

.ARM

Description

Selects the Arm instruction set for following instructions.

See also

.THUMB

.CODE

Select instruction set.

Syntax

.CODE 16
.CODE 32

Description

Selects the Arm or Thumb instruction set according to operand.

Example

SEGGER Assembler V2.10    www.segger.com
GNU_CODE.s - Assembled Thu Nov  7 11:46:23 2019

   1                                    .TEXT
   2                                 
   3                                    .CODE 16
   4                                 
   5             00000000 0120           MOVS R0, #1
   6             00000002 4018           ADDS R0, R0, R1
   7                                 
   8                                    .CODE 32
   9                                 
  10             00000004 0100B0E3       MOVS R0, #1
  11             00000008 010090E0       ADDS R0, R0, R1
  12                                 
  13                                    .END

ASSEMBLY COMPLETE

No errors, no warnings, no remarks

See also

.ARM, .THUMB

.THUMB

Select Thumb instruction set.

Syntax

.THUMB

Description

Selects the Thumb instruction set for following instructions.

See also

.ARM

Section directives

.DATA

Switch to data section

Syntax

.DATA

Description

Switches to the .data section.

.BSS

Switch to bss section

Syntax

.BSS

Description

Switches to the .bss section.

.TEXT

Switch to text section

Syntax

.TEXT

Description

Switches to the .text section.

.RODATA

Switch to data section

Syntax

.RODATA

Description

Switches to the .rodata section.

Symbol directives

.GLOBL, .GLOBAL, .EXTERN

Set external symbol binding.

Syntax

.GLOBL name, name
.GLOBAL name, name
.EXTERN name, name

Description

Defines all symbols in the symbol list to have global binding so that they are externally visible.

.LOCAL

Set local symbol binding.

Syntax

.LOCAL name, name

Description

Defines all symbols in the symbol list to have local binding so that they are not externally visible.

.WEAK

Set weak symbol binding.

Syntax

.WEAK name, name

Description

Defines all symbols in the symbol list to have weak binding so that they can be overridden when linked.

.HIDDEN

Set symbol visibility to hidden.

Syntax

.HIDDEN name, name

Description

Defines all symbols in the symbol list to have hidden visibility and is stored as STV_HIDDEN in the st_other member of the ELF symbol table entry.

.PROTECTED

Set symbol visibility to protected.

Syntax

.PROTECTED name, name

Description

Defines all symbols in the symbol list to have protected visibility and is stored as STV_PROTECTED in the st_other member of the ELF symbol table entry.

.INTERNAL

Set symbol visibility to internal.

Syntax

.INTERNAL name, name

Description

Defines all symbols in the symbol list to have internal visibility and is stored as STV_INTERNAL in the st_other member of the ELF symbol table entry.

Data allocation directives

.BYTE, .ASCII

Allocate 8-bit data.

Syntax

.BYTE expr, expr
.ASCII expr, expr

Description

Place the initialized 8-bit values in the expression list into memory at the location counter.

Example

SEGGER Assembler V2.10    www.segger.com
GNU_BYTE.s - Assembled Thu Nov  7 11:46:23 2019

   1                                    .DATA
   2                                 
   3             00000000 4120736D      .BYTE "A small list of primes:"
                 00000004 616C6C20
                 00000008 6C697374
                 0000000C 206F6620
                 00000010 7072696D
                 00000014 65733A
   4             00000017 02030507      .BYTE 2, 3, 5, 7, 11, 13
                 0000001B 0B0D
   5                                 
   6                                    .END

ASSEMBLY COMPLETE

No errors, no warnings, no remarks

See also

.STRING, .ASCIZ

.STRING, .ASCIZ

Allocate string data.

Syntax

.STRING expr, expr
.ASCIZ expr, expr

Description

Place the initialized string values in the expression list into memory at the location counter, each string followed by a trailing zero byte.

Example

SEGGER Assembler V2.10    www.segger.com
GNU_STRING.s - Assembled Thu Nov  7 11:46:23 2019

   1                                    .DATA
   2                                 
   3                                     @ String is terminated by a zero byte
   4             00000000 49742073      .STRING "It simply works!"
                 00000004 696D706C
                 00000008 7920776F
                 0000000C 726B7321
                 00000010 00
   5                                 
   6                                     @ Each string is terminated by a zero byte
   7             00000011 53454747      .STRING "SEGGER", "The Embedded Experts"
                 00000015 45520054
                 00000019 68652045
                 0000001D 6D626564
                 00000021 64656420
                 00000025 45787065
                 00000029 72747300
   8                                 
   9                                    .END

ASSEMBLY COMPLETE

No errors, no warnings, no remarks

See also

.BYTE, .ASCII

.2BYTE

Allocate 16-bit data.

Syntax

.2BYTE expr, expr

Description

Place the initialized 16-bit values in the expression list into memory at the location counter.

These directives do not force the location counter to be halfword aligned when placing the data, and no warning diagnostic is issued when the location counter is not correctly aligned.

Example

SEGGER Assembler V2.10    www.segger.com
GNU_2BYTE.s - Assembled Thu Nov  7 11:46:23 2019

   1                                    .DATA
   2                                 
   3                                     @ Data that is correctly aligned
   4             00000000 DEADBEEF      .2BYTE 0xADDE, 0xEFBE, 0xDEAD, 0xBEEF
                 00000004 ADDEEFBE
   5                                 
   6                                     @ Data that is not aligned on a halfword
   7             00000008               .SPACE 1
   8             00000009 DEADBEEF      .2BYTE 0xADDE, 0xEFBE, 0xDEAD, 0xBEEF
                 0000000D ADDEEFBE
   9                                 
  10                                    .END

ASSEMBLY COMPLETE

No errors, no warnings, no remarks

See also

.HWORD, .SHORT

.4BYTE

Allocate 32-bit data.

Syntax

.4BYTE expr, expr

Description

Place the initialized 32-bit values in the expression list into memory at the location counter.

These directives do not force the location counter to be word aligned when placing the data, and do not issue a warning diagnostic when the location counter is not correctly aligned.

Example

SEGGER Assembler V2.10    www.segger.com
GNU_4BYTE.s - Assembled Thu Nov  7 11:46:23 2019

   1                                    .DATA
   2                                 
   3                                     @ Data that is correctly aligned
   4             00000000 DEADBEEF      .4BYTE 0xEFBEADDE, 0xDEADBEEF
                 00000004 EFBEADDE
   5                                 
   6                                     @ Data that is not aligned on a word
   7             00000008               .SPACE 1
   8             00000009 DEADBEEF      .4BYTE 0xEFBEADDE, 0xDEADBEEF
                 0000000D EFBEADDE
   9                                 
  10                                    .END

ASSEMBLY COMPLETE

No errors, no warnings, no remarks

See also

.WORD, .INT, .LONG

.HWORD, .SHORT

Allocate 16-bit data.

Syntax

.HWORD expr, expr
.SHORT expr, expr

Description

Place the initialized 16-bit values in the expression list into memory at the location counter.

These directives do not force the location counter to be halfword aligned when placing the data, but a warning diagnostic is issued when the location counter is not correctly aligned.

Example

SEGGER Assembler V2.10    www.segger.com
GNU_HWORD.s - Assembled Thu Nov  7 11:46:23 2019

   1                                    .DATA
   2                                 
   3                                     @ Data that is correctly aligned
   4             00000000 DEADBEEF      .HWORD 0xADDE, 0xEFBE, 0xDEAD, 0xBEEF
                 00000004 ADDEEFBE
   5                                 
   6                                     @ Data that is not aligned on a halfword
   7             00000008               .SPACE 1
   8             00000009 DEADBEEF      .HWORD 0xADDE, 0xEFBE, 0xDEAD, 0xBEEF
                 0000000D ADDEEFBE
   9                                 
  10                                    .END

DIAGNOSTICS

GNU_HWORD.s:8: warning: 16-bit data does not fall on natural alignment at address 00000009
GNU_HWORD.s:8: warning: 16-bit data does not fall on natural alignment at address 0000000B
GNU_HWORD.s:8: warning: 16-bit data does not fall on natural alignment at address 0000000D
GNU_HWORD.s:8: warning: 16-bit data does not fall on natural alignment at address 0000000F

ASSEMBLY COMPLETE

No errors, 4 warnings, no remarks

See also

.2BYTE

.WORD, .INT, .LONG

Allocate 32-bit data.

Syntax

.WORD expr, expr
.INT expr, expr
.LONG expr, expr

Description

Place the initialized 32-bit values in the expression list into memory at the location counter.

These directives do not force the location counter to be word aligned when placing the data, but a warning diagnostic is issued when the location counter is not correctly aligned.

Example

SEGGER Assembler V2.10    www.segger.com
GNU_WORD.s - Assembled Thu Nov  7 11:46:23 2019

   1                                    .DATA
   2                                 
   3                                     @ Data that is correctly aligned
   4             00000000 DEADBEEF      .WORD 0xEFBEADDE, 0xDEADBEEF
                 00000004 EFBEADDE
   5                                 
   6                                     @ Data that is not aligned on a word
   7             00000008               .SPACE 1
   8             00000009 DEADBEEF      .WORD 0xEFBEADDE, 0xDEADBEEF
                 0000000D EFBEADDE
   9                                 
  10                                    .END

DIAGNOSTICS

GNU_WORD.s:8: warning: 32-bit data does not fall on natural alignment at address 00000009
GNU_WORD.s:8: warning: 32-bit data does not fall on natural alignment at address 0000000D

ASSEMBLY COMPLETE

No errors, 2 warnings, no remarks

See also

.4BYTE

.INST

Allocate 16-bit or 32-bit instruction.

Syntax

.INST expr, expr

Description

Place the initialized values in the expression list into memory at the location counter as instruction codes. For values that fit into 16 bits, a 16-bit instruction is generated, and for others a 32-bit instruction is generated.

.INST.N

Allocate 16-bit instruction.

Syntax

.INST.N expr, expr

Description

Place the initialized 16-bit values in the expression list into memory at the location counter as instruction codes.

.INST.W

Allocate 32-bit instruction.

Syntax

.INST.W expr, expr

Description

Place the initialized 32-bit values in the expression list into memory at the location counter as instruction codes.

Section directives

.ALIGN

Align location counter.

Syntax

.ALIGN align-power, fill-value, max-bytes

Description

The align-power expression, which must be absolute, is the power of two to align the location counter to. An align-power of 3, for instance, will ensure that the location counter is a multiple of 23, i.e. 8.

The optional fill-value defines the filler byte to use when aligning the location counter. If omitted, a default value of is selected: the default value for code sections is a nop instruction and for other sections it is zero.

The optional max-bytes defines the maximum number of bytes inserted to align the location counter. If more than max-bytes bytes are required for alignment, no alignment is performed.

.P2ALIGN, .P2ALIGNW, .P2ALIGNL

Align location counter.

Syntax

.P2ALIGN align-power, fill-value, max-bytes
.P2ALIGNW align-power, fill-value, max-bytes
.P2ALIGNL align-power, fill-value, max-bytes

Description

The align-power expression, which must be absolute, is the power of two to align the location counter to. An align-power of 3, for instance, will ensure that the location counter is a multiple of 23, i.e. 8.

The optional fill-value defines the filler value to use when aligning the location counter. If omitted, a default value of is selected: the default value for code sections is a nop instruction and for other sections it is zero. If it is specified, the fill value is a one-byte pattern for .P2ALIGN, a two-byte pattern for .P2ALIGNW, and a 4-byte pattern for .P2ALIGNL.

The optional max-bytes defines the maximum number of bytes inserted to align the location counter. If more than max-bytes bytes are required for alignment, no alignment is performed.

Listing directives

.LIST

Turn on listing.

Syntax

.LIST

Description

Each line subsequently assembled will be printed to the listing file.

.NOLIST

Turn off listing.

Syntax

.LIST

Description

Each line subsequently assembled will be not be printed to the listing file.

.TITLE

Set listing title.

Syntax

.TITLE string-expr

Description

Sets the title that is shown at the top of each page in the listing.

.SUBTTL

Set listing subtitle.

Syntax

.SUBTTL string-expr

Description

Sets the subtitle that is shown below the title at the top of each page in the listing.

Arm syntax

Mode directives

CODE16

Select Thumb instruction set.

Syntax

CODE16

Description

Selects the Thumb instruction set for following instructions.

Example

SEGGER Assembler V2.10    www.segger.com
ARM_CODE16.s - Assembled Thu Nov  7 11:46:23 2019

   1                                     AREA |.text|, CODE
   2                                 
   3                                     CODE16
   4                                 
   5             00000000 0120           MOVS R0, #1
   6             00000002 4018           ADDS R0, R0, R1
   7                                 
   8                                     END

ASSEMBLY COMPLETE

No errors, no warnings, no remarks

See also

CODE32

CODE32

Select Arm instruction set.

Syntax

CODE32

Description

Selects the Arm instruction set for following instructions.

Example

SEGGER Assembler V2.10    www.segger.com
ARM_CODE32.s - Assembled Thu Nov  7 11:46:23 2019

   1                                     AREA |.text|, CODE
   2                                 
   3                                     CODE32
   4                                 
   5             00000000 0100B0E3       MOVS R0, #1
   6             00000004 010090E0       ADDS R0, R0, R1
   7                                 
   8                                     END

ASSEMBLY COMPLETE

No errors, no warnings, no remarks

See also

CODE16

Listing directives

TTL

Set listing title.

Syntax

TTL open-string

Description

Sets the title that is shown at the top of each page in the listing.

SUBT

Set listing subtitle.

Syntax

SUBT open-string

Description

Sets the subtitle that is shown below the title at the top of each page in the listing.

IAR syntax

Mode directives

ARM, CODE32

Select Arm instruction set.

Syntax

ARM
CODE32

Description

Selects the Arm instruction set for following instructions.

See also

THUMB, CODE16

CODE

Select default instruction set.

Syntax

CODE

Description

Selects the Arm or Thumb instruction set according to that specified on the command line by the -mthumb or -marm options. If no instruction set is specified on the command line, the instruction defaults to Thumb.

THUMB, CODE16

Select Thumb instruction set.

Syntax

THUMB
CODE16

Description

Selects the Thumb instruction set for following instructions.

See also

ARM, CODE32

Data allocation directives

DC8, DCB

Allocate 8-bit data.

Syntax

DC8 expr, expr
DCB expr, expr

Description

Place the initialized 8-bit values in the expression list into memory at the location counter.

Example

SEGGER Assembler V2.10    www.segger.com
IAR_DC8.s - Assembled Thu Nov  7 11:46:23 2019

   1                                     SECTION `.data`:DATA(2)
   2                                 
   3             00000000 4120736D       DCB "A small list of primes:"
                 00000004 616C6C20
                 00000008 6C697374
                 0000000C 206F6620
                 00000010 7072696D
                 00000014 65733A
   4             00000017 02030507       DC8  2, 3, 5, 7, 11, 13
                 0000001B 0B0D
   5                                 
   6                                     END

ASSEMBLY COMPLETE

No errors, no warnings, no remarks

DC16, DCW

Allocate 16-bit data.

Syntax

DC16 expr, expr
DCW expr, expr

Description

Place the initialized 16-bit values in the expression list into memory at the location counter.

DC24

Allocate 24-bit data.

Syntax

DC24 expr, expr

Description

Place the initialized 32-bit values in the expression list into memory at the location counter.

DC32, DCD

Allocate 32-bit data.

Syntax

DC32 expr, expr
DCD expr, expr

Description

Place the initialized 32-bit values in the expression list into memory at the location counter.

DCI16, DCIW

Allocate 16-bit instruction.

Syntax

DCI16 expr, expr
DCIW expr, expr

Description

Place the initialized 16-bit values in the expression list into memory at the location counter as instruction codes.

DCI32, DCID

Allocate 32-bit instruction.

Syntax

DCI32 expr, expr
DCID expr, expr

Description

Place the initialized 32-bit values in the expression list into memory at the location counter as instruction codes.

DS8, DS

Allocate space for 8-bit data.

Syntax

DS8 expr
DS expr

Description

Allocate space for expr 8-bit bytes. For zero-data sections such as .bss, the space is allocated; for sections that have content, such as .text and .data, the allocated space is initialized with zero bytes.

DS16, DSW

Allocate space for 16-bit data.

Syntax

DS16 expr
DSW expr

Description

Allocate space for expr 16-bit elements. For zero-data sections such as .bss, the space is allocated; for sections that have content, such as .text and .data, the allocated space is initialized with zero bytes.

DS24

Allocate space for 24-bit data.

Syntax

DS24 expr

Description

Allocate space for expr 24-bit elements. For zero-data sections such as .bss, the space is allocated; for sections that have content, such as .text and .data, the allocated space is initialized with zero bytes.

DS32, DSD

Allocate space for 32-bit data.

Syntax

DS32 expr
DSD expr

Description

Allocate space for expr 32-bit elements. For zero-data sections such as .bss, the space is allocated; for sections that have content, such as .text and .data, the allocated space is initialized with zero bytes.

Instructions

Arm instructions

ADC

Description

Add with carry

Thumb syntax (16-bit, v4T)

ADC Rd, Rn [1]

Thumb syntax (32-bit, v6T2)

ADC Rd, Rn, #const [2]
ADC Rd, Rn, Rm, shift [3]
ADCS Rd, Rn, #const [2]
ADCS Rd, Rn, Rm, shift [3]

Arm syntax (v4T)

ADC Rd, Rn, #const [4]
ADC Rd, Rn, Rm, shift [5]
ADCS Rd, Rn, #const [4]
ADCS Rd, Rn, Rm, shift [5]

Notes

[1] Rd, Rn must be R0R7; ordering Rd, Rn, Rd is also permitted
[2] Rd, RnPC; Rd, RnSP; const is one of $00xx00xx, $xx00xx00, $xxxxxxxx, $xx LSL 024
[3] Rd, Rn, RmPC; Rd, Rn, RmSP; shift is one of LSL #031, LSR #132, ASR #132, RRX
[4] Rd, RnPC; Rd, RnSP; const is $xx ROR 2n
[5] Rd, Rn, RmPC; Rd, Rn, RmSP; shift is one of LSL #031/Rs, LSR #132/Rs, ASR #132/Rs, ROR #131/Rs, RRX

ADD

Description

Add

Thumb syntax (16-bit, v4T)

ADD Rd, Rn [1]
ADD Rd, Rn, Rm [2]
ADD Rd, #0255 [3]
ADD Rd, Rn, #07 [4]
ADD SP, SP, #0508 [5]
ADD Rd, SP, #01020 [6]
ADD Rd, PC, #01020 [6]

Thumb syntax (32-bit, v6T2)

ADD Rd, Rn, #04095 [7]
ADD Rd, Rn, #const [8]
ADD Rd, Rn, Rm, shift [9]
ADDS Rd, Rn, #const [8]
ADDS Rd, Rn, Rm, shift [9]

Arm syntax (v4T)

ADD Rd, Rn, #const [10]
ADD Rd, Rn, Rm, shift [11]
ADD Rd, SP, Rm, shift [12]
ADDS Rd, Rn, #const [13]
ADDS Rd, Rn, Rm, shift [11]
ADDS Rd, SP, Rm, shift [12]

Notes

[1] ordering Rd, Rn, Rd is also permitted
[2] Rd, Rn, Rm must be R0R7
[3] Rd must be R0R7
[4] Rd, Rn must be R0R7
[5] offset a multiple of 4
[6] Rd must be R0R7; offset a multiple of 4
[7] RdPC; RdSP
[8] Rd, RnPC; Rd, RnSP; const is one of $00xx00xx, $xx00xx00, $xxxxxxxx, $xx LSL 024
[9] Rd, Rn, RmPC; Rd, Rn, RmSP; shift is one of LSL #031, LSR #132, ASR #132, RRX
[10] RdSP; const is $xx ROR 2n
[11] Rd, RmPC; Rd, RmSP; shift is one of LSL #031/Rs, LSR #132/Rs, ASR #132/Rs, ROR #131/Rs, RRX
[12] Rd, RmPC; RmSP; shift is one of LSL #031/Rs, LSR #132/Rs, ASR #132/Rs, ROR #131/Rs, RRX
[13] RdPC; RdSP; const is $xx ROR 2n

ADDW

Description

Add

Thumb syntax (16-bit, v6T2)

ADDW Rd, PC, #01020 [1]

Thumb syntax (32-bit, v6T2)

ADDW Rd, Rn, #04095 [2]

Notes

[1] Rd must be R0R7; offset a multiple of 4
[2] RdPC; RdSP

AND

Description

Bitwise and

Thumb syntax (16-bit, v4T)

AND Rd, Rn [1]

Thumb syntax (32-bit, v6T2)

AND Rd, Rn, #const [2]
AND Rd, Rn, Rm, shift [3]
ANDS Rd, Rn, #const [2]
ANDS Rd, Rn, Rm, shift [3]

Arm syntax (v4T)

AND Rd, Rn, #const [4]
AND Rd, Rn, Rm, shift [5]
ANDS Rd, Rn, #const [4]
ANDS Rd, Rn, Rm, shift [5]

Notes

[1] Rd, Rn must be R0R7; ordering Rd, Rn, Rd is also permitted
[2] Rd, RnPC; Rd, RnSP; const is one of $00xx00xx, $xx00xx00, $xxxxxxxx, $xx LSL 024
[3] Rd, Rn, RmPC; Rd, Rn, RmSP; shift is one of LSL #031, LSR #132, ASR #132, RRX
[4] Rd, RnPC; Rd, RnSP; const is $xx ROR 2n
[5] Rd, Rn, RmPC; Rd, Rn, RmSP; shift is one of LSL #031/Rs, LSR #132/Rs, ASR #132/Rs, ROR #131/Rs, RRX

ASR

Description

Arithmetic shift right

Thumb syntax (16-bit, v4T)

ASR Rd, Rn [1]
ASR Rd, Rn, #132 [1]

Thumb syntax (32-bit, v6T2)

ASR Rd, Rn, Rm [2]
ASR Rd, Rn, #132 [3]
ASRS Rd, Rn, Rm [2]
ASRS Rd, Rn, #132 [3]

Arm syntax (v4T)

ASR Rd, Rn, Rm [4]
ASR Rd, Rn, #132
ASRS Rd, Rn, Rm [4]
ASRS Rd, Rn, #132

Notes

[1] Rd, Rn must be R0R7
[2] Rd, Rn, RmPC; Rd, Rn, RmSP
[3] Rd, RnPC; Rd, RnSP
[4] Rd, Rn, RmPC

B

Description

Branch

Thumb syntax (16-bit, v4T)

B Label [1]

Thumb syntax (32-bit, v6T2)

B Label

Arm syntax (v4T)

B Label

Notes

[1] not permitted in an IT block

BCC

Description

Branch if no carry

Thumb syntax (16-bit, v4T)

BCC Label [1]

Thumb syntax (32-bit, v6T2)

BCC Label [1]

Notes

[1] not permitted in an IT block

BCS

Description

Branch if carry

Thumb syntax (16-bit, v4T)

BCS Label [1]

Thumb syntax (32-bit, v6T2)

BCS Label [1]

Notes

[1] not permitted in an IT block

BEQ

Description

Branch if equal

Thumb syntax (16-bit, v4T)

BEQ Label [1]

Thumb syntax (32-bit, v6T2)

BEQ Label [1]

Notes

[1] not permitted in an IT block

BFC

Description

Bitfield clear

Thumb syntax (32-bit, v6T2)

BFC Rd, #lsb, #width [1]

Arm syntax (v6T2)

BFC Rd, #lsb, #width [1]

Notes

[1] Rd, RnPC; Rd, RnSP

BFI

Description

Bitfield insert

Thumb syntax (32-bit, v6T2)

BFI Rd, Rn, #lsb, #width [1]

Arm syntax (v6T2)

BFI Rd, Rn, #lsb, #width [1]

Notes

[1] Rd, RnPC; Rd, RnSP

BGE

Description

Branch if greater or equal

Thumb syntax (16-bit, v4T)

BGE Label [1]

Thumb syntax (32-bit, v6T2)

BGE Label [1]

Notes

[1] not permitted in an IT block

BGT

Description

Branch if greater

Thumb syntax (16-bit, v4T)

BGT Label [1]

Thumb syntax (32-bit, v6T2)

BGT Label [1]

Notes

[1] not permitted in an IT block

BHI

Description

Branch if greater

Thumb syntax (16-bit, v4T)

BHI Label [1]

Thumb syntax (32-bit, v6T2)

BHI Label [1]

Notes

[1] not permitted in an IT block

BHS

Description

Branch if carry

Thumb syntax (16-bit, v4T)

BHS Label [1]

Thumb syntax (32-bit, v6T2)

BHS Label [1]

Notes

[1] not permitted in an IT block

BIC

Description

Bitwise clear

Thumb syntax (16-bit, v4T)

BIC Rd, Rn [1]

Thumb syntax (32-bit, v6T2)

BIC Rd, Rn, #const [2]
BIC Rd, Rn, Rm, shift [3]
BICS Rd, Rn, #const [2]
BICS Rd, Rn, Rm, shift [3]

Arm syntax (v4T)

BIC Rd, Rn, #const [4]
BIC Rd, Rn, Rm, shift [5]
BICS Rd, Rn, #const [4]
BICS Rd, Rn, Rm, shift [5]

Notes

[1] Rd, Rn must be R0R7
[2] Rd, RnPC; Rd, RnSP; const is one of $00xx00xx, $xx00xx00, $xxxxxxxx, $xx LSL 024
[3] Rd, Rn, RmPC; Rd, Rn, RmSP; shift is one of LSL #031, LSR #132, ASR #132, RRX
[4] Rd, RnPC; const is $xx ROR 2n
[5] Rd, Rn, RmPC; shift is one of LSL #031/Rs, LSR #132/Rs, ASR #132/Rs, ROR #131/Rs, RRX

BKPT

Description

Breakpoint

Thumb syntax (16-bit, v5T)

BKPT #0255

Arm syntax (v5T)

BKPT Rd, #065535

BL

Description

Branch link

Thumb syntax (32-bit, v4T)

BL Label

Arm syntax (v4T)

BL Label

BLE

Description

Branch if less than or equal

Thumb syntax (16-bit, v4T)

BLE Label [1]

Thumb syntax (32-bit, v6T2)

BLE Label [1]

Notes

[1] not permitted in an IT block

BLO

Description

Branch if no carry

Thumb syntax (16-bit, v4T)

BLO Label [1]

Thumb syntax (32-bit, v6T2)

BLO Label [1]

Notes

[1] not permitted in an IT block

BLS

Thumb syntax (16-bit, v4T)

BLS Label [1]

Thumb syntax (32-bit, v6T2)

BLS Label [1]

Notes

[1] not permitted in an IT block

BLT

Description

Branch is less than

Thumb syntax (16-bit, v4T)

BLT Label [1]

Thumb syntax (32-bit, v6T2)

BLT Label [1]

Notes

[1] not permitted in an IT block

BLX

Description

Branch link and exchange

Thumb syntax (16-bit, v5T)

BLX Rd [1]

Thumb syntax (32-bit, v4T)

BLX Label

Arm syntax (v4T)

BLX Rd [1]
BLX Label

Notes

[1] RdPC; RdSP

BMI

Description

Branch if negative

Thumb syntax (16-bit, v4T)

BMI Label [1]

Thumb syntax (32-bit, v6T2)

BMI Label [1]

Notes

[1] not permitted in an IT block

BNE

Description

Branch if not equal

Thumb syntax (16-bit, v4T)

BNE Label [1]

Thumb syntax (32-bit, v6T2)

BNE Label [1]

Notes

[1] not permitted in an IT block

BPL

Description

Branch is nonnegative

Thumb syntax (16-bit, v4T)

BPL Label [1]

Thumb syntax (32-bit, v6T2)

BPL Label [1]

Notes

[1] not permitted in an IT block

BVC

Description

Branch if no overflow

Thumb syntax (16-bit, v4T)

BVC Label [1]

Thumb syntax (32-bit, v6T2)

BVC Label [1]

Notes

[1] not permitted in an IT block

BVS

Description

Branch is overflow

Thumb syntax (16-bit, v4T)

BVS Label [1]

Thumb syntax (32-bit, v6T2)

BVS Label [1]

Notes

[1] not permitted in an IT block

BX

Description

Branch and exchange

Thumb syntax (16-bit, v4T)

BX Rd [1]

Arm syntax (v4T)

BX Rd

Notes

[1] RdPC; RdSP

BXJ

Description

Branch and change to Jazelle state

Thumb syntax (32-bit, v6J)

BXJ Rd [1]

Arm syntax (v6J)

BXJ Rd [1]

Notes

[1] RdPC; RdSP

CBNZ

Description

Branch if nonzero

Thumb syntax (16-bit, v6T2)

CBNZ Rd, Label [1]

Notes

[1] not permitted in an IT block

CBZ

Description

Branch if zero

Thumb syntax (16-bit, v6T2)

CBZ Rd, Label [1]

Notes

[1] not permitted in an IT block

CDP

Description

Coprocessor data operation

Thumb syntax (32-bit, v6T2)

CDP Pn, [#]015, CRx, CRy, CRz

Arm syntax (v6T2)

CDP Pn, [#]015, CRx, CRy, CRz

CDP2

Description

Coprocessor data operation

Thumb syntax (32-bit, v6T2)

CDP2 Pn, [#]015, CRx, CRy, CRz

Arm syntax (v6T2)

CDP2 Pn, [#]015, CRx, CRy, CRz

CLREX

Description

Clear exclusive

Thumb syntax (32-bit, v6T2)

CLREX

Arm syntax (v6K)

CLREX

CLZ

Description

Count leading zeros

Thumb syntax (32-bit, v6T2)

CLZ Rd, Rn [1]

Arm syntax (v5T)

CLZ Rd, Rn [2]

Notes

[1] Rd, RnPC; Rd, RnSP
[2] Rd, RnPC

CMN

Description

Compare negated

Thumb syntax (16-bit, v4T)

CMN Rn, Rm [1]

Thumb syntax (32-bit, v6T2)

CMN Rn, #const [2]
CMN Rn, Rm, shift [3]

Arm syntax (v4T)

CMN Rn, #const [4]
CMN Rn, Rm, shift [5]

Notes

[1] Rn, Rm must be R0R7
[2] RnPC; const is one of $00xx00xx, $xx00xx00, $xxxxxxxx, $xx LSL 024
[3] Rn, RmPC; RmSP; shift is one of LSL #031, LSR #132, ASR #132, RRX
[4] RnPC; const is $xx ROR 2n
[5] Rn, RmPC; RmSP; shift is one of LSL #031/Rs, LSR #132/Rs, ASR #132/Rs, ROR #131/Rs, RRX

CMP

Description

Compare

Thumb syntax (16-bit, v4T)

CMP Rn, Rm [1]
CMP Rn, #0255 [2]

Thumb syntax (32-bit, v6T2)

CMP Rn, #const [3]
CMP Rn, Rm, shift [4]

Arm syntax (v4T)

CMP Rn, #const [5]
CMP Rn, Rm, shift [6]

Notes

[1] Rn, RmPC; RmSP
[2] Rn must be R0R7
[3] RnPC; const is one of $00xx00xx, $xx00xx00, $xxxxxxxx, $xx LSL 024
[4] Rn, RmPC; RmSP; shift is one of LSL #031, LSR #132, ASR #132, RRX
[5] RnPC; const is $xx ROR 2n
[6] Rn, RmPC; RmSP; shift is one of LSL #031/Rs, LSR #132/Rs, ASR #132/Rs, ROR #131/Rs, RRX

CPS

Description

Change processor state

Thumb syntax (32-bit, v)

CPS #031 [1]

Arm syntax (v)

CPS #031 [1]

Notes

[1] not permitted in an IT block

CPSID

Description

Change processor state

Thumb syntax (16-bit, v6)

CPSID flags [1]

Thumb syntax (32-bit, v)

CPSID flags [1]
CPSID flags, #031 [1]

Arm syntax (v6)

CPSID flags [2]
CPSID flags, #031 [2]

Notes

[1] flags is any combination of ’A’, ’I’, and ’F’; not permitted in an IT block
[2] flags is any combination of ’A’, ’I’, and ’F’

CPSIE

Description

Change processor state

Thumb syntax (16-bit, v6)

CPSIE flags [1]

Thumb syntax (32-bit, v)

CPSIE flags [1]
CPSIE flags, #031 [1]

Arm syntax (v6)

CPSIE flags [2]
CPSIE flags, #031 [2]

Notes

[1] flags is any combination of ’A’, ’I’, and ’F’; not permitted in an IT block
[2] flags is any combination of ’A’, ’I’, and ’F’

CPY

Description

Copy

Thumb syntax (16-bit, v6)

CPY Rd, Rn

Arm syntax (v4T)

CPY Rd, Rn

CRC32B

Description

CRC32 checksum byte

Thumb syntax (32-bit, v)

CRC32B Rd, Rn, Rm

Arm syntax (v)

CRC32B Rd, Rn, Rm

CRC32CB

Description

CRC32-C checksum byte

Thumb syntax (32-bit, v)

CRC32CB Rd, Rn, Rm

Arm syntax (v)

CRC32CB Rd, Rn, Rm

CRC32CH

Description

CRC32-C checksum halfword

Thumb syntax (32-bit, v)

CRC32CH Rd, Rn, Rm

Arm syntax (v)

CRC32CH Rd, Rn, Rm

CRC32CW

Description

CRC32-C checksum word

Thumb syntax (32-bit, v)

CRC32CW Rd, Rn, Rm

Arm syntax (v)

CRC32CW Rd, Rn, Rm

CRC32H

Description

CRC32 checksum halfword

Thumb syntax (32-bit, v)

CRC32H Rd, Rn, Rm

Arm syntax (v)

CRC32H Rd, Rn, Rm

CRC32W

Description

CRC32 checksum word

Thumb syntax (32-bit, v)

CRC32W Rd, Rn, Rm

Arm syntax (v)

CRC32W Rd, Rn, Rm

DBG

Description

Debug

Thumb syntax (32-bit, v6T2)

DBG #015

Arm syntax (v6)

DBG #015

DCPS1

Description

Debug switch to exception level 1

Thumb syntax (32-bit, v)

DCPS1

DCPS2

Description

Debug switch to exception level 2

Thumb syntax (32-bit, v)

DCPS2

DCPS3

Description

Debug switch to exception level 3

Thumb syntax (32-bit, v)

DCPS3

DMB

Description

Data memory barrier

Thumb syntax (32-bit, v6-M)

DMB #015

Arm syntax (v)

DMB #015

DSB

Description

Data synchronization barrier

Thumb syntax (32-bit, v6-M)

DSB #015

Arm syntax (v)

DSB #015

EOR

Description

Bitwise exclusive-or

Thumb syntax (16-bit, v4T)

EOR Rd, Rn [1]

Thumb syntax (32-bit, v6T2)

EOR Rd, Rn, #const [2]
EOR Rd, Rn, Rm, shift [3]
EORS Rd, Rn, #const [2]
EORS Rd, Rn, Rm, shift [3]

Arm syntax (v4T)

EOR Rd, Rn, #const [4]
EOR Rd, Rn, Rm, shift [5]
EORS Rd, Rn, #const [4]
EORS Rd, Rn, Rm, shift [5]

Notes

[1] Rd, Rn must be R0R7; ordering Rd, Rn, Rd is also permitted
[2] Rd, RnPC; Rd, RnSP; const is one of $00xx00xx, $xx00xx00, $xxxxxxxx, $xx LSL 024
[3] Rd, Rn, RmPC; Rd, Rn, RmSP; shift is one of LSL #031, LSR #132, ASR #132, RRX
[4] Rd, RnPC; Rd, RnSP; const is $xx ROR 2n
[5] Rd, Rn, RmPC; Rd, Rn, RmSP; shift is one of LSL #031/Rs, LSR #132/Rs, ASR #132/Rs, ROR #131/Rs, RRX

ERET

Description

Exception return

Thumb syntax (32-bit, v)

ERET

Arm syntax (v)

ERET

ESB

Description

Exception synchronization barrier

Thumb syntax (32-bit, v)

ESB

Arm syntax (v)

ESB

HLT

Description

Halt

Thumb syntax (16-bit, v)

HLT #0…63

Arm syntax (v)

HLT Rd, #065535

HVC

Description

Hypervisor call

Thumb syntax (32-bit, v)

HVC #065535

Arm syntax (v)

HVC Rd, #065535

ISB

Description

Instruction synchronization barrier

Thumb syntax (32-bit, v6-M)

ISB #015

Arm syntax (v)

ISB #015

IT

Description

If-Then

Thumb syntax (16-bit, v6T2)

IT

ITE

Description

If-Then-Else

Thumb syntax (16-bit, v6T2)

ITE

ITEE

Description

If-Then-Else-Else

Thumb syntax (16-bit, v6T2)

ITEE

ITEEE

Description

If-Then-Else-Else-Else

Thumb syntax (16-bit, v6T2)

ITEEE

ITEET

Description

If-Then-Else-Else-Then

Thumb syntax (16-bit, v6T2)

ITEET

ITET

Description

If-Then-Else-Then

Thumb syntax (16-bit, v6T2)

ITET

ITETE

Description

If-Then-Else-Then-Else

Thumb syntax (16-bit, v6T2)

ITETE

ITETT

Description

If-Then-Else-Then-Then

Thumb syntax (16-bit, v6T2)

ITETT

ITT

Description

If-Then-Then

Thumb syntax (16-bit, v6T2)

ITT

ITTE

Description

If-Then-Then-Else

Thumb syntax (16-bit, v6T2)

ITTE

ITTEE

Description

If-Then-Then-Else-Else

Thumb syntax (16-bit, v6T2)

ITTEE

ITTET

Description

If-Then-Then-Else-Then

Thumb syntax (16-bit, v6T2)

ITTET

ITTT

Description

If-Then-Then-Then

Thumb syntax (16-bit, v6T2)

ITTT

ITTTE

Description

If-Then-Then-Then-Else

Thumb syntax (16-bit, v6T2)

ITTTE

ITTTT

Description

If-Then-Then-Then-Then

Thumb syntax (16-bit, v6T2)

ITTTT

LDA

Description

Load-acquire word

Thumb syntax (32-bit, v)

LDA Rd, [Rn] [1]

Arm syntax (v)

LDA Rd, [Rn] [1]

Notes

[1] Rd, RnPC; RdSP

LDAB

Description

Load-acquire byte

Thumb syntax (32-bit, v)

LDAB Rd, [Rn] [1]

Arm syntax (v)

LDAB Rd, [Rn] [1]

Notes

[1] Rd, RnPC; RdSP

LDAEX

Description

Load-acquire word exclusive

Thumb syntax (32-bit, v)

LDAEX Rd, [Rn] [1]

Arm syntax (v)

LDAEX Rd, [Rn] [1]

Notes

[1] Rd, RnPC; RdSP

LDAEXB

Description

Load-acquire byte exclusive

Thumb syntax (32-bit, v)

LDAEXB Rd, [Rn] [1]

Arm syntax (v)

LDAEXB Rd, [Rn] [1]

Notes

[1] Rd, RnPC; RdSP

LDAEXD

Description

Load-acquire doubleword exclusive

Thumb syntax (32-bit, v)

LDAEXD Rd1, Rd2, [Rn] [1]

Arm syntax (v)

LDAEXD Rd1, Rd2, [Rn] [2]

Notes

[1] Rd1, Rd2, RnPC; Rd1Rd2
[2] Rd1, Rd2, RnPC; Rd1Rd2; Rd1 must be an evennumbered register; Rd2 must be the following oddnumbered register

LDAEXH

Description

Load-acquire halfword exclusive

Thumb syntax (32-bit, v)

LDAEXH Rd, [Rn] [1]

Arm syntax (v)

LDAEXH Rd, [Rn] [1]

Notes

[1] Rd, RnPC; RdSP

LDAH

Description

Load-acquire halfword

Thumb syntax (32-bit, v)

LDAH Rd, [Rn] [1]

Arm syntax (v)

LDAH Rd, [Rn] [1]

Notes

[1] Rd, RnPC; RdSP

LDM

Description

Load multiple

Thumb syntax (16-bit, v4T)

LDM SP!, {Rn, Rm}
LDM Rd, {Rn, Rm} [1]
LDM Rd, {Rn, Rm} [2]
LDM Rd!, {Rn, Rm} [1]

Thumb syntax (32-bit, v6T2)

LDM Rd, {Rn, Rm} [2]
LDM Rd!, {Rn, Rm} [2]

Arm syntax (v4T)

LDM Rd, {Rn, Rm} [2]
LDM Rd!, {Rn, Rm} [2]

Notes

[1] Rd must be R0R7; RdPC
[2] RdPC

LDMDA

Description

Load multiple decrement after

Thumb syntax (16-bit, v4T)

LDMDA Rd, {Rn, Rm}

Thumb syntax (32-bit, v6T2)

LDMDA Rd, {Rn, Rm}
LDMDA Rd!, {Rn, Rm} [1]

Arm syntax (v4T)

LDMDA Rd, {Rn, Rm} [1]
LDMDA Rd!, {Rn, Rm} [1]

Notes

[1] RdPC

LDMDB

Description

Load multiple decrement before

Thumb syntax (32-bit, v6T2)

LDMDB Rd, {Rn, Rm} [1]
LDMDB Rd!, {Rn, Rm} [1]

Arm syntax (v4T)

LDMDB Rd, {Rn, Rm} [1]
LDMDB Rd!, {Rn, Rm} [1]

Notes

[1] RdPC

LDMEA

Description

Load multiple empty ascending

Thumb syntax (32-bit, v6T2)

LDMEA Rd, {Rn, Rm} [1]
LDMEA Rd!, {Rn, Rm} [1]

Arm syntax (v4T)

LDMEA Rd, {Rn, Rm} [1]
LDMEA Rd!, {Rn, Rm} [1]

Notes

[1] RdPC

LDMED

Description

Load multiple empty descending

Thumb syntax (16-bit, v4T)

LDMED Rd, {Rn, Rm}

Thumb syntax (32-bit, v6T2)

LDMED Rd, {Rn, Rm}
LDMED Rd!, {Rn, Rm} [1]

Arm syntax (v4T)

LDMED Rd, {Rn, Rm} [1]
LDMED Rd!, {Rn, Rm} [1]

Notes

[1] RdPC

LDMFA

Description

Load multiple full ascending

Thumb syntax (16-bit, v4T)

LDMFA Rd, {Rn, Rm}

Thumb syntax (32-bit, v6T2)

LDMFA Rd, {Rn, Rm}
LDMFA Rd!, {Rn, Rm} [1]

Arm syntax (v4T)

LDMFA Rd, {Rn, Rm} [1]
LDMFA Rd!, {Rn, Rm} [1]

Notes

[1] RdPC

LDMFD

Description

Load multiple full descending

Thumb syntax (16-bit, v4T)

LDMFD SP!, {Rn, Rm}
LDMFD Rd, {Rn, Rm} [1]
LDMFD Rd, {Rn, Rm} [2]
LDMFD Rd!, {Rn, Rm} [1]

Thumb syntax (32-bit, v6T2)

LDMFD Rd, {Rn, Rm} [2]
LDMFD Rd!, {Rn, Rm} [2]

Arm syntax (v4T)

LDMFD Rd, {Rn, Rm} [2]
LDMFD Rd!, {Rn, Rm} [2]

Notes

[1] Rd must be R0R7; RdPC
[2] RdPC

LDMIA

Description

Load multiple increment after

Thumb syntax (16-bit, v4T)

LDMIA SP!, {Rn, Rm}
LDMIA Rd, {Rn, Rm} [1]
LDMIA Rd, {Rn, Rm} [2]
LDMIA Rd!, {Rn, Rm} [1]

Thumb syntax (32-bit, v6T2)

LDMIA Rd, {Rn, Rm} [2]
LDMIA Rd!, {Rn, Rm} [2]

Arm syntax (v4T)

LDMIA Rd, {Rn, Rm} [2]
LDMIA Rd!, {Rn, Rm} [2]

Notes

[1] Rd must be R0R7; RdPC
[2] RdPC

LDMIB

Description

Load multiple increment before

Thumb syntax (16-bit, v4T)

LDMIB Rd, {Rn, Rm}

Thumb syntax (32-bit, v6T2)

LDMIB Rd, {Rn, Rm}
LDMIB Rd!, {Rn, Rm} [1]

Arm syntax (v4T)

LDMIB Rd, {Rn, Rm} [1]
LDMIB Rd!, {Rn, Rm} [1]

Notes

[1] RdPC

LDR

Description

Load word

Thumb syntax (16-bit, v4T)

LDR Rd, [Rn, #0124] [1]
LDR Rd, [SP, #01020] [2]
LDR Rd, [PC, #01020] [2]
LDR Rd, [Rn, Rm] [3]
LDR Rd, #Label

Thumb syntax (32-bit, v6T2)

LDR Rd, [Rn, #2554095]
LDR Rd, [PC, #40954095]
LDR Rd, [Rn, #255255]! [4]
LDR Rd, [Rn], #255255 [4]
LDR Rd, [Rn, Rm] [5]
LDR Rd, [Rn, Rm, LSL #13] [6]
LDR Rd, #Label

Arm syntax (v4T)

LDR Rd, [Rn, #40954095]
LDR Rd, [Rn, #40954095]! [4]
LDR Rd, [Rn], #40954095 [4]
LDR Rd, [Rn], ±Rm, shift [7]
LDR Rd, [Rn, ±Rm] [8]
LDR Rd, [Rn, ±Rm]! [7]

Notes

[1] Rd, Rn must be R0R7; offset a multiple of 4
[2] offset a multiple of 4
[3] Rd, Rn, Rm must be R0R7
[4] RnPC; RdRn
[5] Rn, RmPC; RmSP
[6] Rn, RmPC; RmSP; LSL #0 is also permitted
[7] Rn, RmPC; RmSP; RdRn
[8] RmPC; RmSP

LDRB

Description

Load byte

Thumb syntax (16-bit, v4T)

LDRB Rd, [Rn, #031] [1]
LDRB Rd, [Rn, Rm] [2]

Thumb syntax (32-bit, v6T2)

LDRB Rd, [Rn, #2554095] [3]
LDRB Rd, [PC, #40954095] [3]
LDRB Rd, [Rn, #255255]! [4]
LDRB Rd, [Rn], #255255 [4]
LDRB Rd, [Rn, Rm, LSL #13] [5]

Arm syntax (v4T)

LDRB Rd, [Rn, #40954095] [3]
LDRB Rd, [Rn, #40954095]! [4]
LDRB Rd, [Rn], #40954095 [4]
LDRB Rd, [Rn], ±Rm, shift [6]
LDRB Rd, [Rn, ±Rm] [7]
LDRB Rd, [Rn, ±Rm]! [6]

Notes

[1] Rd, Rn must be R0R7; RdPC; RdSP
[2] Rd, Rn, Rm must be R0R7
[3] RdPC; RdSP
[4] Rd, RnPC; RdSP; RdRn
[5] Rd, Rn, RmPC; Rd, RmSP; LSL #0 is also permitted
[6] Rd, Rn, RmPC; Rd, RmSP; RdRn
[7] Rd, RmPC; Rd, RmSP

LDRBT

Description

Load byte, user mode

Thumb syntax (32-bit, v6T2)

LDRBT Rd, [Rn, #0255] [1]

Arm syntax (v4T)

LDRBT Rd, [Rn], #40954095 [2]
LDRBT Rd, [Rn], ±Rm, shift [3]

Notes

[1] Rd, RnPC; RdSP
[2] Rd, RnPC; RdSP; RdRn
[3] Rd, Rn, RmPC; Rd, RmSP; RdRn

LDRD

Description

Load doubleword

Thumb syntax (32-bit, v6T2)

LDRD Rd1, Rd2, [Rn, #10201020] [1]
LDRD Rd1, Rd2, [Rn, #10201020]! [2]
LDRD Rd1, Rd2, [Rn], #10201020 [2]

Arm syntax (v)

LDRD Rd1, Rd2, [Rn, #255255] [3]
LDRD Rd1, Rd2, [Rn, #255255]! [4]
LDRD Rd1, Rd2, [Rn], #255255 [4]
LDRD Rd1, Rd2, [Rn, ±Rm] [5]
LDRD Rd1, Rd2, [Rn, ±Rm]! [6]
LDRD Rd1, Rd2, [Rn], ±Rm [6]

Notes

[1] Rd1, Rd2 ≠ PC; Rd1, Rd2 ≠ SP; Rd1Rd2; offset a multiple of 4
[2] Rd1, Rd2, RnPC; Rd1, Rd2 ≠ SP; Rd1Rd2 ≠ Rn; offset a multiple of 4
[3] Rd1, Rd2 ≠ PC; Rd2 ≠ SP; Rd1Rd2; Rd1 must be an evennumbered register; Rd2 must be the following oddnumbered register
[4] Rd1, Rd2, RnPC; Rd2 ≠ SP; Rd1Rd2 ≠ Rn; Rd1 must be an evennumbered register; Rd2 must be the following oddnumbered register
[5] Rd1, Rd2, RmPC; Rd2, RmSP; Rd1Rd2 ≠ Rm; Rd1 must be an evennumbered register; Rd2 must be the following oddnumbered register
[6] Rd1, Rd2, Rn, RmPC; Rd2, RmSP; Rd1Rd2 ≠ Rn; Rd1Rd2 ≠ Rm; Rd1 must be an evennumbered register; Rd2 must be the following oddnumbered register

LDREX

Description

Load word exclusive

Thumb syntax (32-bit, v6T2)

LDREX Rd, [Rn, #01020] [1]

Arm syntax (v6)

LDREX Rd, [Rn] [2]

Notes

[1] Rd, RnPC; RdSP; offset a multiple of 4
[2] Rd, RnPC; RdSP

LDREXB

Description

Load byte exclusive

Thumb syntax (32-bit, v6T2)

LDREXB Rd, [Rn] [1]

Arm syntax (v6)

LDREXB Rd, [Rn] [1]

Notes

[1] Rd, RnPC; RdSP

LDREXD

Description

Load doubleword exclusive

Thumb syntax (32-bit, v)

LDREXD Rd1, Rd2, [Rn] [1]

Arm syntax (v)

LDREXD Rd1, Rd2, [Rn] [2]

Notes

[1] Rd1, Rd2, RnPC; Rd1, Rd2 ≠ SP; Rd1Rd2
[2] Rd1, Rd2, RnPC; Rd1, Rd2 ≠ SP; Rd1Rd2; Rd1 must be an evennumbered register; Rd2 must be the following oddnumbered register

LDREXH

Description

Load halfword exclusive

Thumb syntax (32-bit, v6T2)

LDREXH Rd, [Rn] [1]

Arm syntax (v6)

LDREXH Rd, [Rn] [1]

Notes

[1] Rd, RnPC; RdSP

LDRH

Description

Load halfword

Thumb syntax (16-bit, v4T)

LDRH Rd, [Rn, #062] [1]
LDRH Rd, [Rn, Rm] [2]

Thumb syntax (32-bit, v6T2)

LDRH Rd, [Rn, #2554095] [3]
LDRH Rd, [PC, #40954095] [4]
LDRH Rd, [Rn, #255255]! [5]
LDRH Rd, [Rn], #255255 [5]
LDRH Rd, [Rn, Rm] [6]
LDRH Rd, [Rn, Rm, LSL #13] [7]

Arm syntax (v4T)

LDRH Rd, [Rn, #255255] [4]
LDRH Rd, [Rn, #255255]! [5]
LDRH Rd, [Rn], #255255 [5]
LDRH Rd, [Rn, ±Rm] [8]
LDRH Rd, [Rn, ±Rm]! [9]
LDRH Rd, [Rn], ±Rm [9]

Notes

[1] Rd, Rn must be R0R7; offset a multiple of 2
[2] Rd, Rn, Rm must be R0R7
[3] Rd, RnPC; RdSP
[4] RdPC; RdSP
[5] Rd, RnPC; RdSP; RdRn
[6] Rd, Rn, RmPC; Rd, RmSP
[7] Rd, Rn, RmPC; Rd, RmSP; LSL #0 is also permitted
[8] Rd, RmPC; Rd, RmSP
[9] Rd, Rn, RmPC; Rd, RmSP; RdRn

LDRHT

Description

Load halfword, user mode

Thumb syntax (32-bit, v6T2)

LDRHT Rd, [Rn, #0255] [1]

Arm syntax (v6T2)

LDRHT Rd, [Rn], #255255 [2]
LDRHT Rd, [Rn], ±Rm [3]

Notes

[1] Rd, RnPC; RdSP
[2] Rd, RnPC; RdSP; RdRn
[3] Rd, Rn, RmPC; Rd, RmSP; RdRn

LDRSB

Description

Load sign-extended byte

Thumb syntax (16-bit, v4T)

LDRSB Rd, [Rn, Rm] [1]

Thumb syntax (32-bit, v6T2)

LDRSB Rd, [Rn, #2554095] [2]
LDRSB Rd, [PC, #40954095] [3]
LDRSB Rd, [Rn, #255255]! [4]
LDRSB Rd, [Rn], #255255 [4]
LDRSB Rd, [Rn, Rm, LSL #13] [5]

Arm syntax (v4T)

LDRSB Rd, [Rn, #255255] [3]
LDRSB Rd, [Rn, #255255]! [4]
LDRSB Rd, [Rn], #255255 [4]
LDRSB Rd, [Rn, ±Rm] [6]
LDRSB Rd, [Rn, ±Rm]! [7]
LDRSB Rd, [Rn], ±Rm [7]

Notes

[1] Rd, Rn, Rm must be R0R7
[2] Rd, RnPC; RdSP
[3] RdPC; RdSP
[4] Rd, RnPC; RdSP; RdRn
[5] Rd, Rn, RmPC; Rd, RmSP; LSL #0 is also permitted
[6] Rd, RmPC; Rd, RmSP
[7] Rd, Rn, RmPC; Rd, RmSP; RdRn

LDRSBT

Description

Load sign-extended byte, user mode

Thumb syntax (32-bit, v6T2)

LDRSBT Rd, [Rn, #0255] [1]

Arm syntax (v6T2)

LDRSBT Rd, [Rn], #255255 [2]
LDRSBT Rd, [Rn], ±Rm [3]

Notes

[1] Rd, RnPC; RdSP
[2] Rd, RnPC; RdSP; RdRn
[3] Rd, Rn, RmPC; Rd, RmSP; RdRn

LDRSH

Description

Load sign-extended halfword

Thumb syntax (16-bit, v4T)

LDRSH Rd, [Rn, Rm] [1]

Thumb syntax (32-bit, v6T2)

LDRSH Rd, [Rn, #2554095] [2]
LDRSH Rd, [PC, #40954095] [3]
LDRSH Rd, [Rn, #255255]! [2]
LDRSH Rd, [Rn], #255255 [2]
LDRSH Rd, [Rn, Rm, LSL #13] [4]

Arm syntax (v4T)

LDRSH Rd, [Rn, #255255] [3]
LDRSH Rd, [Rn, #255255]! [2]
LDRSH Rd, [Rn], #255255 [2]
LDRSH Rd, [Rn, ±Rm] [5]
LDRSH Rd, [Rn, ±Rm]! [6]
LDRSH Rd, [Rn], ±Rm [6]

Notes

[1] Rd, Rn, Rm must be R0R7
[2] Rd, RnPC; RdSP; RdRn
[3] RdPC; RdSP
[4] Rd, Rn, RmPC; Rd, RmSP; LSL #0 is also permitted
[5] Rd, RmPC; Rd, RmSP
[6] Rd, Rn, RmPC; Rd, RmSP; RdRn

LDRSHT

Description

Load sign-extended halfword, user mode

Thumb syntax (32-bit, v6T2)

LDRSHT Rd, [Rn, #0255] [1]

Arm syntax (v6T2)

LDRSHT Rd, [Rn], #255255 [2]
LDRSHT Rd, [Rn], ±Rm [3]

Notes

[1] Rd, RnPC; RdSP
[2] Rd, RnPC; RdSP; RdRn
[3] Rd, Rn, RmPC; Rd, RmSP; RdRn

LDRT

Description

Load word, user mode

Thumb syntax (32-bit, v6T2)

LDRT Rd, [Rn, #0255] [1]

Arm syntax (v4T)

LDRT Rd, [Rn], #40954095 [2]
LDRT Rd, [Rn], ±Rm, shift [3]

Notes

[1] Rd, RnPC; RdSP
[2] Rd, RnPC; RdSP; RdRn
[3] Rd, Rn, RmPC; Rd, RmSP; RdRn

LSL

Description

Logical shift left

Thumb syntax (16-bit, v4T)

LSL Rd, Rn [1]
LSL Rd, Rn, #031 [1]

Thumb syntax (32-bit, v6T2)

LSL Rd, Rn, Rm [2]
LSL Rd, Rn, #031 [3]
LSLS Rd, Rn, Rm [2]
LSLS Rd, Rn, #031 [3]

Arm syntax (v4T)

LSL Rd, Rn, Rm [2]
LSL Rd, Rn, #031 [3]
LSLS Rd, Rn, Rm [2]
LSLS Rd, Rn, #031 [3]

Notes

[1] Rd, Rn must be R0R7
[2] Rd, Rn, RmPC; Rd, Rn, RmSP
[3] Rd, RnPC; Rd, RnSP

LSR

Description

Logical shift right

Thumb syntax (16-bit, v4T)

LSR Rd, Rn [1]
LSR Rd, Rn, #132 [1]

Thumb syntax (32-bit, v6T2)

LSR Rd, Rn, Rm [2]
LSR Rd, Rn, #132 [3]
LSRS Rd, Rn, Rm [2]
LSRS Rd, Rn, #132 [3]

Arm syntax (v4T)

LSR Rd, Rn, Rm [2]
LSR Rd, Rn, #132 [3]
LSRS Rd, Rn, Rm [2]
LSRS Rd, Rn, #132 [3]

Notes

[1] Rd, Rn must be R0R7
[2] Rd, Rn, RmPC; Rd, Rn, RmSP
[3] Rd, RnPC; Rd, RnSP

MCR

Description

Move register to coprocessor

Thumb syntax (32-bit, v6T2)

MCR Pn, [#]07, Rn, CRx, CRy, [[#]07] [1]

Arm syntax (v4T)

MCR Pn, [#]07, Rn, CRx, CRy, [[#]07] [1]

Notes

[1] RmPC; RmSP

MCR2

Description

Move register to coprocessor

Thumb syntax (32-bit, v6T2)

MCR2 Pn, [#]07, Rn, CRx, CRy, [[#]07] [1]

Arm syntax (v5T)

MCR2 Pn, [#]07, Rn, CRx, CRy, [[#]07] [1]

Notes

[1] RmPC; RmSP

MCRR

Description

Move registers to coprocessor

Thumb syntax (32-bit, v6T2)

MCRR Pn, [#]015, Rn, Rm, CRx, CRy

Arm syntax (v4T)

MCRR Pn, [#]015, Rn, Rm, CRx, CRy

MCRR2

Description

Move registers to coprocessor

Thumb syntax (32-bit, v6T2)

MCRR2 Pn, [#]015, Rn, Rm, CRx, CRy [1]

Arm syntax (v6T2)

MCRR2 Pn, [#]015, Rn, Rm, CRx, CRy [1]

Notes

[1] RnPC; RnSP

MLA

Description

Multiply and add

Thumb syntax (32-bit, v6T2)

MLA Rd, Rn, Rm, Ra [1]

Arm syntax (v4T)

MLA Rd, Rn, Rm, Ra [2]
MLAS Rd, Rn, Rm, Ra [2]

Notes

[1] Rd, Rn, Rm, RaPC; Rd, Rn, Rm, RaSP
[2] Rd, Rn, Rm, RaPC; RdRn

MLS

Description

Multiply and subtract

Thumb syntax (32-bit, v6T2)

MLS Rd, Rn, Rm, Ra [1]

Arm syntax (v6T2)

MLS Rd, Rn, Rm, Ra [1]

Notes

[1] Rd, Rn, Rm, RaPC; Rd, Rn, Rm, RaSP

MOV

Description

Move

Thumb syntax (16-bit, v4T)

MOV *** Unknown (0)
MOV Rd, Rn
MOV Rd, Rn [1]
MOV Rd, #0 [2]

Thumb syntax (32-bit, v6T2)

MOV Rd, #065535 [3]
MOV Rd, #const [4]
MOV Rd, Rn, shift [5]
MOVS Rd, #const [4]
MOVS Rd, Rn, shift [6]

Arm syntax (v4T)

MOV Rd, #065535 [3]
MOV Rd, #const [7]
MOV Rd, Rn, shift [8]
MOVS Rd, #const [7]
MOVS Rd, Rn, shift [9]

Notes

[1] Rd, Rn must be R0R7
[2] Rd must be R0R7
[3] RdPC; RdSP
[4] RdPC; RdSP; const is one of $00xx00xx, $xx00xx00, $xxxxxxxx, $xx LSL 024
[5] Rd, RnPC; shift is one of LSL #031, LSR #132, ASR #132, RRX
[6] Rd, RnPC; Rd, RnSP; shift is one of LSL #031, LSR #132, ASR #132, RRX
[7] RdPC; RdSP; const is $xx ROR 2n
[8] shift is one of LSL #031/Rs, LSR #132/Rs, ASR #132/Rs, ROR #131/Rs, RRX
[9] Rd, RnPC; Rd, RnSP; shift is one of LSL #031/Rs, LSR #132/Rs, ASR #132/Rs, ROR #131/Rs, RRX

MOVS

Thumb syntax (32-bit, v6T2)

MOVS Rd, #const [1]
MOVS Rd, Rn, shift [2]

Arm syntax (v4T)

MOVS Rd, #const [3]
MOVS Rd, Rn, shift [4]

Notes

[1] RdPC; RdSP; const is one of $00xx00xx, $xx00xx00, $xxxxxxxx, $xx LSL 024
[2] Rd, RnPC; Rd, RnSP; shift is one of LSL #031, LSR #132, ASR #132, RRX
[3] RdPC; RdSP; const is $xx ROR 2n
[4] Rd, RnPC; Rd, RnSP; shift is one of LSL #031/Rs, LSR #132/Rs, ASR #132/Rs, ROR #131/Rs, RRX

MOVT

Description

Move top

Thumb syntax (32-bit, v6T2)

MOVT Rd, #065535 [1]

Notes

[1] RdPC; RdSP

MOVW

Description

Move

Thumb syntax (32-bit, v6T2)

MOVW Rd, #065535 [1]

Arm syntax (v6T2)

MOVW Rd, #065535 [1]

Notes

[1] RdPC; RdSP

MRC

Description

Move coprocessor to register

Thumb syntax (32-bit, v6T2)

MRC Pn, [#]07, Rn, CRx, CRy, [[#]07] [1]

Arm syntax (v4T)

MRC Pn, [#]07, Rn, CRx, CRy, [[#]07]

Notes

[1] RmPC; RmSP

MRC2

Description

Move coprocessor to register

Thumb syntax (32-bit, v6T2)

MRC2 Pn, [#]07, Rn, CRx, CRy, [[#]07] [1]

Arm syntax (v5T)

MRC2 Pn, [#]07, Rn, CRx, CRy, [[#]07]

Notes

[1] RmSP

MRRC

Description

Move coprocessor to registers

Thumb syntax (32-bit, v6T2)

MRRC Pn, [#]015, Rn, Rm, CRx, CRy

Arm syntax (v4T)

MRRC Pn, [#]015, Rn, Rm, CRx, CRy

MRRC2

Description

Move coprocessor to registers

Thumb syntax (32-bit, v6T2)

MRRC2 Pn, [#]015, Rn, Rm, CRx, CRy [1]

Arm syntax (v6T2)

MRRC2 Pn, [#]015, Rn, Rm, CRx, CRy [1]

Notes

[1] RnPC; RnSP

MRS

Description

Move system register to register

Thumb syntax (32-bit, v6T2)

MRS Rd, SysReg [1]

Arm syntax (v4T)

MRS Rd, SysReg [1]

Notes

[1] RdPC; RdSP

MSR

Description

Move register to system register

Thumb syntax (32-bit, v6T2)

MSR SysReg, Rn [1]

Arm syntax (v4T)

MSR SysReg, Rn [1]
MSR SysReg, #04095

Notes

[1] RnPC; RnSP

MUL

Description

Multiply

Thumb syntax (16-bit, v4T)

MUL Rd, Rn [1]

Thumb syntax (32-bit, v6T2)

MUL Rd, Rn, Rm [2]

Arm syntax (v4T)

MUL Rd, Rn, Rm [3]
MULS Rd, Rn, Rm [3]

Notes

[1] Rd, Rn must be R0R7; ordering Rd, Rn, Rd is also permitted
[2] Rd, Rn, RmPC; Rd, Rn, RmSP
[3] Rd, Rn, RmPC; RdRn

MVN

Description

Move not

Thumb syntax (16-bit, v4T)

MVN Rd, Rn [1]

Thumb syntax (32-bit, v6T2)

MVN Rd, #const [2]
MVN Rd, Rn, shift [3]
MVNS Rd, #const [2]
MVNS Rd, Rn, shift [3]

Arm syntax (v4T)

MVN Rd, #const [4]
MVN Rd, Rn, shift [5]
MVNS Rd, #const [4]
MVNS Rd, Rn, shift [5]

Notes

[1] Rd, Rn must be R0R7
[2] RdPC; RdSP; const is one of $00xx00xx, $xx00xx00, $xxxxxxxx, $xx LSL 024
[3] Rd, RnPC; Rd, RnSP; shift is one of LSL #031, LSR #132, ASR #132, RRX
[4] Rd, RnPC; Rd, RnSP; const is $xx ROR 2n
[5] Rd, RnPC; Rd, RnSP; shift is one of LSL #031/Rs, LSR #132/Rs, ASR #132/Rs, ROR #131/Rs, RRX

NEG

Description

Negate

Thumb syntax (16-bit, v4T)

NEG Rd, Rn [1]

Thumb syntax (32-bit, v6T2)

NEG Rd, Rn [2]
NEGS Rd, Rn [2]

Arm syntax (v4T)

NEG Rd, Rn [2]
NEGS Rd, Rn [2]

Notes

[1] Rd, Rn must be R0R7
[2] Rd, RnPC; Rd, RnSP

NOP

Description

No operation

Thumb syntax (16-bit, v6-M)

NOP

Thumb syntax (32-bit, v6T2)

NOP

Arm syntax (v4T)

NOP

ORN

Description

Bitwise or-not

Thumb syntax (32-bit, v6T2)

ORN Rd, Rn, #const [1]
ORN Rd, Rn, Rm, shift [2]
ORNS Rd, Rn, #const [1]
ORNS Rd, Rn, Rm, shift [2]

Notes

[1] Rd, RnPC; Rd, RnSP; const is one of $00xx00xx, $xx00xx00, $xxxxxxxx, $xx LSL 024
[2] Rd, Rn, RmPC; Rd, Rn, RmSP; shift is one of LSL #031, LSR #132, ASR #132, RRX

ORR

Description

Bitwise or

Thumb syntax (16-bit, v4T)

ORR Rd, Rn [1]

Thumb syntax (32-bit, v6T2)

ORR Rd, Rn, #const [2]
ORR Rd, Rn, Rm, shift [3]
ORRS Rd, Rn, #const [2]
ORRS Rd, Rn, Rm, shift [3]

Arm syntax (v4T)

ORR Rd, Rn, #const [4]
ORR Rd, Rn, Rm, shift [5]
ORRS Rd, Rn, #const [4]
ORRS Rd, Rn, Rm, shift [5]

Notes

[1] Rd, Rn must be R0R7; ordering Rd, Rn, Rd is also permitted
[2] Rd, RnPC; Rd, RnSP; const is one of $00xx00xx, $xx00xx00, $xxxxxxxx, $xx LSL 024
[3] Rd, Rn, RmPC; Rd, Rn, RmSP; shift is one of LSL #031, LSR #132, ASR #132, RRX
[4] Rd, RnPC; Rd, RnSP; const is $xx ROR 2n
[5] Rd, Rn, RmPC; Rd, Rn, RmSP; shift is one of LSL #031/Rs, LSR #132/Rs, ASR #132/Rs, ROR #131/Rs, RRX

PKHBT

Description

Pack halfword

Thumb syntax (32-bit, v7E-M)

PKHBT Rd, Rn, Rm, shift [1]

Arm syntax (v)

PKHBT Rd, Rn, Rm, shift [2]

Notes

[1] Rd, Rn, RmPC; Rd, Rn, RmSP; shift is one of LSL #031, LSR #132, ASR #132, RRX
[2] Rd, Rn, RmPC; Rd, Rn, RmSP; shift is one of LSL #031/Rs, LSR #132/Rs, ASR #132/Rs, ROR #131/Rs, RRX

PKHTB

Description

Pack halfword

Thumb syntax (32-bit, v7E-M)

PKHTB Rd, Rn, Rm, shift [1]

Arm syntax (v)

PKHTB Rd, Rn, Rm, shift [2]

Notes

[1] Rd, Rn, RmPC; Rd, Rn, RmSP; shift is one of LSL #031, LSR #132, ASR #132, RRX
[2] Rd, Rn, RmPC; Rd, Rn, RmSP; shift is one of LSL #031/Rs, LSR #132/Rs, ASR #132/Rs, ROR #131/Rs, RRX

PLD

Description

Preload data

Thumb syntax (32-bit, v6T2)

PLD [Rd, #40954095]
PLD Rd, [Rn, Rm, LSL #13] [1]

Arm syntax (v6T2)

PLD [Rd, #40954095]

Notes

[1] RdPC; LSL #0 is also permitted

PLDW

Description

Preload data, write invalidate

Thumb syntax (32-bit, v6T2)

PLDW [Rd, #2554095] [1]
PLDW Rd, [Rn, Rm, LSL #13] [2]

Arm syntax (v6T2)

PLDW [Rd, #40954095] [1]

Notes

[1] RdPC
[2] RdPC; LSL #0 is also permitted

PLI

Description

Preload instruction

Thumb syntax (32-bit, v6T2)

PLI [Rd, #40954095]
PLI Rd, [Rn, Rm, LSL #13] [1]

Arm syntax (v6T2)

PLI [Rd, #40954095]

Notes

[1] RdPC; LSL #0 is also permitted

POP

Description

Pop registers

Thumb syntax (16-bit, v4T)

POP {Rn, Rm}

Thumb syntax (32-bit, v6T2)

POP {Rn, Rm}

Arm syntax (v4T)

POP {Rn, Rm}

PUSH

Description

Push registers

Thumb syntax (16-bit, v4T)

PUSH {Rn, Rm}

Thumb syntax (32-bit, v6T2)

PUSH {Rn, Rm}

Arm syntax (v4T)

PUSH {Rn, Rm}

QADD

Description

Signed add, saturating

Thumb syntax (32-bit, v6T2)

QADD Rd, Rn, Rm [1]

Arm syntax (v)

QADD Rd, Rn, Rm [1]

Notes

[1] Rd, Rn, RmPC; Rd, Rn, RmSP

QADD16

Description

Signed parallel halfword add, saturating

Thumb syntax (32-bit, v6T2)

QADD16 Rd, Rn, Rm [1]

Arm syntax (v6T2)

QADD16 Rd, Rn, Rm [1]

Notes

[1] Rd, Rn, RmPC; Rd, Rn, RmSP

QADD8

Description

Signed parallel byte add, saturating

Thumb syntax (32-bit, v6T2)

QADD8 Rd, Rn, Rm [1]

Arm syntax (v6T2)

QADD8 Rd, Rn, Rm [1]

Notes

[1] Rd, Rn, RmPC; Rd, Rn, RmSP

QASX

Thumb syntax (32-bit, v6T2)

QASX Rd, Rn, Rm [1]

Arm syntax (v6T2)

QASX Rd, Rn, Rm [1]

Notes

[1] Rd, Rn, RmPC; Rd, Rn, RmSP

QDADD

Thumb syntax (32-bit, v6T2)

QDADD Rd, Rn, Rm [1]

Arm syntax (v)

QDADD Rd, Rn, Rm [1]

Notes

[1] Rd, Rn, RmPC; Rd, Rn, RmSP

QDSUB

Thumb syntax (32-bit, v6T2)

QDSUB Rd, Rn, Rm [1]

Arm syntax (v)

QDSUB Rd, Rn, Rm [1]

Notes

[1] Rd, Rn, RmPC; Rd, Rn, RmSP

QSAX

Thumb syntax (32-bit, v6T2)

QSAX Rd, Rn, Rm [1]

Arm syntax (v6T2)

QSAX Rd, Rn, Rm [1]

Notes

[1] Rd, Rn, RmPC; Rd, Rn, RmSP

QSUB

Description

Signed subtract, saturating

Thumb syntax (32-bit, v6T2)

QSUB Rd, Rn, Rm [1]

Arm syntax (v)

QSUB Rd, Rn, Rm [1]

Notes

[1] Rd, Rn, RmPC; Rd, Rn, RmSP

QSUB16

Description

Signed parallel halfword subtract, saturating

Thumb syntax (32-bit, v6T2)

QSUB16 Rd, Rn, Rm [1]

Arm syntax (v6T2)

QSUB16 Rd, Rn, Rm [1]

Notes

[1] Rd, Rn, RmPC; Rd, Rn, RmSP

QSUB8

Description

Signed parallel byte subtract, saturating

Thumb syntax (32-bit, v6T2)

QSUB8 Rd, Rn, Rm [1]

Arm syntax (v6T2)

QSUB8 Rd, Rn, Rm [1]

Notes

[1] Rd, Rn, RmPC; Rd, Rn, RmSP

RBIT

Description

Reverse bits

Thumb syntax (32-bit, v6T2)

RBIT Rd, Rn [1]

Arm syntax (v6T2)

RBIT Rd, Rn [1]

Notes

[1] Rd, RnPC; Rd, RnSP

REV

Description

Reverse byte order

Thumb syntax (16-bit, v6)

REV Rd, Rn [1]

Thumb syntax (32-bit, v6T2)

REV Rd, Rn [1]

Arm syntax (v6T2)

REV Rd, Rn [1]

Notes

[1] Rd, RnPC; Rd, RnSP

REV16

Description

Reverse halfword byte order

Thumb syntax (16-bit, v6)

REV16 Rd, Rn [1]

Thumb syntax (32-bit, v6T2)

REV16 Rd, Rn [1]

Arm syntax (v6T2)

REV16 Rd, Rn [1]

Notes

[1] Rd, RnPC; Rd, RnSP

REVSH

Description

Reverse low halfword byte order, sign extend

Thumb syntax (16-bit, v6)

REVSH Rd, Rn [1]

Thumb syntax (32-bit, v6T2)

REVSH Rd, Rn [1]

Arm syntax (v6T2)

REVSH Rd, Rn [1]

Notes

[1] Rd, RnPC; Rd, RnSP

RFE

Description

Return from exception

Thumb syntax (32-bit, v6)

RFE SP [1]
RFE SP! [1]

Arm syntax (v6)

RFE SP [1]
RFE SP! [1]

Notes

[1] RdPC

RFEDA

Description

Return from exception, decrement after

Arm syntax (v6)

RFEDA SP [1]
RFEDA SP! [1]

Notes

[1] RdPC

RFEDB

Description

Return from exception, decrement before

Thumb syntax (32-bit, v6)

RFEDB SP [1]
RFEDB SP! [1]

Arm syntax (v6)

RFEDB SP [1]
RFEDB SP! [1]

Notes

[1] RdPC

RFEIA

Description

Return from exception, increment after

Thumb syntax (32-bit, v6)

RFEIA SP [1]
RFEIA SP! [1]

Arm syntax (v6)

RFEIA SP [1]
RFEIA SP! [1]

Notes

[1] RdPC

RFEIB

Description

Return from exception, increment before

Arm syntax (v6)

RFEIB SP [1]
RFEIB SP! [1]

Notes

[1] RdPC

ROR

Description

Rotate right

Thumb syntax (16-bit, v4T)

ROR Rd, Rn [1]

Thumb syntax (32-bit, v6T2)

ROR Rd, Rn, Rm [2]
ROR Rd, Rn, #131 [3]
RORS Rd, Rn, Rm [2]
RORS Rd, Rn, #131 [3]

Arm syntax (v4T)

ROR Rd, Rn, Rm [2]
ROR Rd, Rn, #131 [3]
RORS Rd, Rn, Rm [2]
RORS Rd, Rn, #131 [3]

Notes

[1] Rd, Rn must be R0R7
[2] Rd, Rn, RmPC; Rd, Rn, RmSP
[3] Rd, RnPC; Rd, RnSP

RRX

Description

Rotate right through carry

Thumb syntax (32-bit, v6T2)

RRX Rd, Rn [1]
RRXS Rd, Rn [1]

Arm syntax (v4T)

RRX Rd, Rn [1]
RRXS Rd, Rn [1]

Notes

[1] Rd, RnPC; Rd, RnSP

RSB

Description

Reverse subtract

Thumb syntax (16-bit, v4T)

RSB Rd, Rn, #0 [1]

Thumb syntax (32-bit, v6T2)

RSB Rd, Rn, #const [2]
RSB Rd, Rn, Rm, shift [3]
RSBS Rd, Rn, #const [2]
RSBS Rd, Rn, Rm, shift [3]

Arm syntax (v4T)

RSB Rd, Rn, #const [4]
RSB Rd, Rn, Rm, shift [5]
RSBS Rd, Rn, #const [4]
RSBS Rd, Rn, Rm, shift [5]

Notes

[1] Rd, Rn must be R0R7
[2] Rd, RnPC; Rd, RnSP; const is one of $00xx00xx, $xx00xx00, $xxxxxxxx, $xx LSL 024
[3] Rd, Rn, RmPC; Rd, Rn, RmSP; shift is one of LSL #031, LSR #132, ASR #132, RRX
[4] Rd, RnPC; Rd, RnSP; const is $xx ROR 2n
[5] Rd, Rn, RmPC; Rd, Rn, RmSP; shift is one of LSL #031/Rs, LSR #132/Rs, ASR #132/Rs, ROR #131/Rs, RRX

RSC

Description

Reverse subtract with carry

Arm syntax (v4T)

RSC Rd, Rn, #const [1]
RSC Rd, Rn, Rm, shift [2]
RSCS Rd, Rn, #const [1]
RSCS Rd, Rn, Rm, shift [2]

Notes

[1] Rd, RnPC; Rd, RnSP; const is $xx ROR 2n
[2] Rd, Rn, RmPC; Rd, Rn, RmSP; shift is one of LSL #031/Rs, LSR #132/Rs, ASR #132/Rs, ROR #131/Rs, RRX

SADD16

Thumb syntax (32-bit, v6T2)

SADD16 Rd, Rn, Rm [1]

Arm syntax (v6T2)

SADD16 Rd, Rn, Rm [1]

Notes

[1] Rd, Rn, RmPC; Rd, Rn, RmSP

SADD8

Thumb syntax (32-bit, v6T2)

SADD8 Rd, Rn, Rm [1]

Arm syntax (v6T2)

SADD8 Rd, Rn, Rm [1]

Notes

[1] Rd, Rn, RmPC; Rd, Rn, RmSP

SASX

Thumb syntax (32-bit, v6T2)

SASX Rd, Rn, Rm [1]

Arm syntax (v6T2)

SASX Rd, Rn, Rm [1]

Notes

[1] Rd, Rn, RmPC; Rd, Rn, RmSP

SBC

Description

Subtract with carry

Thumb syntax (16-bit, v4T)

SBC Rd, Rn [1]

Thumb syntax (32-bit, v6T2)

SBC Rd, Rn, #const [2]
SBC Rd, Rn, Rm, shift [3]
SBCS Rd, Rn, #const [2]
SBCS Rd, Rn, Rm, shift [3]

Arm syntax (v4T)

SBC Rd, Rn, #const [4]
SBC Rd, Rn, Rm, shift [5]
SBCS Rd, Rn, #const [4]
SBCS Rd, Rn, Rm, shift [5]

Notes

[1] Rd, Rn must be R0R7
[2] Rd, RnPC; Rd, RnSP; const is one of $00xx00xx, $xx00xx00, $xxxxxxxx, $xx LSL 024
[3] Rd, Rn, RmPC; Rd, Rn, RmSP; shift is one of LSL #031, LSR #132, ASR #132, RRX
[4] Rd, RnPC; Rd, RnSP; const is $xx ROR 2n
[5] Rd, Rn, RmPC; Rd, Rn, RmSP; shift is one of LSL #031/Rs, LSR #132/Rs, ASR #132/Rs, ROR #131/Rs, RRX

SBFX

Description

Signed bitfield extract

Thumb syntax (32-bit, v6T2)

SBFX Rd, Rn, #lsb, #width [1]

Arm syntax (v6T2)

SBFX Rd, Rn, #lsb, #width [1]

Notes

[1] Rd, RnPC; Rd, RnSP

SDIV

Description

Signed divide

Thumb syntax (32-bit, v7)

SDIV Rd, Rn, Rm [1]

Arm syntax (v)

SDIV Rd, Rn, Rm [1]

Notes

[1] Rd, Rn, RmPC; Rd, Rn, RmSP

SEL

Thumb syntax (32-bit, v6T2)

SEL Rd, Rn, Rm

Arm syntax (v6T2)

SEL Rd, Rn, Rm

SETEND

Description

Set byte order

Thumb syntax (16-bit, v6)

SETEND endian [1]

Arm syntax (v6)

SETEND endian [1]

Notes

[1] endian is ’LE’ or ’BE’; not permitted in an IT block

SETPAN

Thumb syntax (16-bit, v)

SETPAN #01 [1]

Arm syntax (v)

SETPAN #01

Notes

[1] not permitted in an IT block

SEV

Description

Signal event

Thumb syntax (16-bit, v6K)

SEV

Thumb syntax (32-bit, v7)

SEV

Arm syntax (v6K)

SEV

SEVL

Description

Signal event, local

Thumb syntax (16-bit, v)

SEVL

Thumb syntax (32-bit, v)

SEVL

Arm syntax (v)

SEVL

SHADD16

Thumb syntax (32-bit, v6T2)

SHADD16 Rd, Rn, Rm [1]

Arm syntax (v6T2)

SHADD16 Rd, Rn, Rm [1]

Notes

[1] Rd, Rn, RmPC; Rd, Rn, RmSP

SHADD8

Thumb syntax (32-bit, v6T2)

SHADD8 Rd, Rn, Rm [1]

Arm syntax (v6T2)

SHADD8 Rd, Rn, Rm [1]

Notes

[1] Rd, Rn, RmPC; Rd, Rn, RmSP

SHASX

Thumb syntax (32-bit, v6T2)

SHASX Rd, Rn, Rm [1]

Arm syntax (v6T2)

SHASX Rd, Rn, Rm [1]

Notes

[1] Rd, Rn, RmPC; Rd, Rn, RmSP

SHSAX

Thumb syntax (32-bit, v6T2)

SHSAX Rd, Rn, Rm [1]

Arm syntax (v6T2)

SHSAX Rd, Rn, Rm [1]

Notes

[1] Rd, Rn, RmPC; Rd, Rn, RmSP

SHSUB16

Thumb syntax (32-bit, v6T2)

SHSUB16 Rd, Rn, Rm [1]

Arm syntax (v6T2)

SHSUB16 Rd, Rn, Rm [1]

Notes

[1] Rd, Rn, RmPC; Rd, Rn, RmSP

SHSUB8

Thumb syntax (32-bit, v6T2)

SHSUB8 Rd, Rn, Rm [1]

Arm syntax (v6T2)

SHSUB8 Rd, Rn, Rm [1]

Notes

[1] Rd, Rn, RmPC; Rd, Rn, RmSP

SMC

Description

Secure monitor call

Thumb syntax (32-bit, v)

SMC #015

Arm syntax (v)

SMC #015

SMLABB

Description

Signed halfword multiply, word accumulate

Thumb syntax (32-bit, v6T2)

SMLABB Rd, Rn, Rm, Ra [1]

Arm syntax (v6T2)

SMLABB Rd, Rn, Rm, Ra [1]

Notes

[1] Rd, Rn, Rm, RaPC; Rd, Rn, Rm, RaSP

SMLABT

Description

Signed halfword multiply, word accumulate

Thumb syntax (32-bit, v6T2)

SMLABT Rd, Rn, Rm, Ra [1]

Arm syntax (v6T2)

SMLABT Rd, Rn, Rm, Ra [1]

Notes

[1] Rd, Rn, Rm, RaPC; Rd, Rn, Rm, RaSP

SMLAD

Description

Dual 16-bit signed multiply-add

Thumb syntax (32-bit, v6T2)

SMLAD Rd, Rn, Rm, Ra [1]

Arm syntax (v6T2)

SMLAD Rd, Rn, Rm, Ra [1]

Notes

[1] Rd, Rn, Rm, RaPC; Rd, Rn, Rm, RaSP

SMLADX

Thumb syntax (32-bit, v6T2)

SMLADX Rd, Rn, Rm, Ra [1]

Arm syntax (v6T2)

SMLADX Rd, Rn, Rm, Ra [1]

Notes

[1] Rd, Rn, Rm, RaPC; Rd, Rn, Rm, RaSP

SMLAL

Thumb syntax (32-bit, v6T2)

SMLAL Rd, Rn, Rm, Ra [1]

Arm syntax (v4T)

SMLAL Rd, Rn, Rm, Ra [2]
SMLALS Rd, Rn, Rm, Ra [2]

Notes

[1] Rd, Rn, Rm, RaPC; Rd, Rn, Rm, RaSP; RdRn
[2] Rd, Rn, Rm, RaPC; RdRnRm

SMLALBB

Description

Signed halfword multiply, doubleword accumulate

Thumb syntax (32-bit, v6T2)

SMLALBB Rd, Rn, Rm, Ra [1]

Arm syntax (v6T2)

SMLALBB Rd, Rn, Rm, Ra [1]

Notes

[1] Rd, Rn, Rm, RaPC; Rd, Rn, Rm, RaSP; RdRn

SMLALBT

Description

Signed halfword multiply, doubleword accumulate

Thumb syntax (32-bit, v6T2)

SMLALBT Rd, Rn, Rm, Ra [1]

Arm syntax (v6T2)

SMLALBT Rd, Rn, Rm, Ra [1]

Notes

[1] Rd, Rn, Rm, RaPC; Rd, Rn, Rm, RaSP; RdRn

SMLALD

Description

Dual 16-bit signed multiply-add, doubleword accumulate

Thumb syntax (32-bit, v7E-M)

SMLALD Rd, Rn, Rm, Ra [1]

Arm syntax (v6T2)

SMLALD Rd, Rn, Rm, Ra [1]

Notes

[1] Rd, Rn, Rm, RaPC; Rd, Rn, Rm, RaSP; RdRn

SMLALDX

Thumb syntax (32-bit, v7E-M)

SMLALDX Rd, Rn, Rm, Ra [1]

Arm syntax (v6T2)

SMLALDX Rd, Rn, Rm, Ra [1]

Notes

[1] Rd, Rn, Rm, RaPC; Rd, Rn, Rm, RaSP; RdRn

SMLALTB

Description

Signed halfword multiply, doubleword accumulate

Thumb syntax (32-bit, v6T2)

SMLALTB Rd, Rn, Rm, Ra [1]

Arm syntax (v6T2)

SMLALTB Rd, Rn, Rm, Ra [1]

Notes

[1] Rd, Rn, Rm, RaPC; Rd, Rn, Rm, RaSP; RdRn

SMLALTT

Description

Signed halfword multiply, doubleword accumulate

Thumb syntax (32-bit, v6T2)

SMLALTT Rd, Rn, Rm, Ra [1]

Arm syntax (v6T2)

SMLALTT Rd, Rn, Rm, Ra [1]

Notes

[1] Rd, Rn, Rm, RaPC; Rd, Rn, Rm, RaSP; RdRn

SMLATB

Description

Signed halfword multiply, word accumulate

Thumb syntax (32-bit, v6T2)

SMLATB Rd, Rn, Rm, Ra [1]

Arm syntax (v6T2)

SMLATB Rd, Rn, Rm, Ra [1]

Notes

[1] Rd, Rn, Rm, RaPC; Rd, Rn, Rm, RaSP

SMLATT

Description

Signed halfword multiply, word accumulate

Thumb syntax (32-bit, v6T2)

SMLATT Rd, Rn, Rm, Ra [1]

Arm syntax (v6T2)

SMLATT Rd, Rn, Rm, Ra [1]

Notes

[1] Rd, Rn, Rm, RaPC; Rd, Rn, Rm, RaSP

SMLAWB

Description

Signed multiply-accumulate wide

Thumb syntax (32-bit, v6T2)

SMLAWB Rd, Rn, Rm, Ra [1]

Arm syntax (v6T2)

SMLAWB Rd, Rn, Rm, Ra [1]

Notes

[1] Rd, Rn, Rm, RaPC; Rd, Rn, Rm, RaSP

SMLAWT

Description

Signed multiply-accumulate wide

Thumb syntax (32-bit, v6T2)

SMLAWT Rd, Rn, Rm, Ra [1]

Arm syntax (v6T2)

SMLAWT Rd, Rn, Rm, Ra [1]

Notes

[1] Rd, Rn, Rm, RaPC; Rd, Rn, Rm, RaSP

SMLSD

Description

Dual 16-bit signed multiply-subtract

Thumb syntax (32-bit, v6T2)

SMLSD Rd, Rn, Rm, Ra [1]

Arm syntax (v6T2)

SMLSD Rd, Rn, Rm, Ra [1]

Notes

[1] Rd, Rn, Rm, RaPC; Rd, Rn, Rm, RaSP

SMLSDX

Thumb syntax (32-bit, v6T2)

SMLSDX Rd, Rn, Rm, Ra [1]

Arm syntax (v6T2)

SMLSDX Rd, Rn, Rm, Ra [1]

Notes

[1] Rd, Rn, Rm, RaPC; Rd, Rn, Rm, RaSP

SMLSLD

Description

Dual 16-bit signed multiply-subtract, doubleword accumulate

Thumb syntax (32-bit, v6T2)

SMLSLD Rd, Rn, Rm, Ra [1]

Arm syntax (v6T2)

SMLSLD Rd, Rn, Rm, Ra [1]

Notes

[1] Rd, Rn, Rm, RaPC; Rd, Rn, Rm, RaSP; RdRn

SMLSLDX

Thumb syntax (32-bit, v6T2)

SMLSLDX Rd, Rn, Rm, Ra [1]

Arm syntax (v6T2)

SMLSLDX Rd, Rn, Rm, Ra [1]

Notes

[1] Rd, Rn, Rm, RaPC; Rd, Rn, Rm, RaSP; RdRn

SMMLA

Thumb syntax (32-bit, v6T2)

SMMLA Rd, Rn, Rm, Ra [1]

Arm syntax (v6T2)

SMMLA Rd, Rn, Rm, Ra [1]

Notes

[1] Rd, Rn, Rm, RaPC; Rd, Rn, Rm, RaSP

SMMLAR

Thumb syntax (32-bit, v6T2)

SMMLAR Rd, Rn, Rm, Ra [1]

Arm syntax (v6T2)

SMMLAR Rd, Rn, Rm, Ra [1]

Notes

[1] Rd, Rn, Rm, RaPC; Rd, Rn, Rm, RaSP

SMMLS

Thumb syntax (32-bit, v6T2)

SMMLS Rd, Rn, Rm, Ra [1]

Arm syntax (v6T2)

SMMLS Rd, Rn, Rm, Ra [1]

Notes

[1] Rd, Rn, Rm, RaPC; Rd, Rn, Rm, RaSP

SMMLSR

Thumb syntax (32-bit, v6T2)

SMMLSR Rd, Rn, Rm, Ra [1]

Arm syntax (v6T2)

SMMLSR Rd, Rn, Rm, Ra [1]

Notes

[1] Rd, Rn, Rm, RaPC; Rd, Rn, Rm, RaSP

SMMUL

Thumb syntax (32-bit, v6T2)

SMMUL Rd, Rn, Rm [1]

Arm syntax (v6T2)

SMMUL Rd, Rn, Rm [1]

Notes

[1] Rd, Rn, RmPC; Rd, Rn, RmSP

SMMULR

Thumb syntax (32-bit, v6T2)

SMMULR Rd, Rn, Rm [1]

Arm syntax (v6T2)

SMMULR Rd, Rn, Rm [1]

Notes

[1] Rd, Rn, RmPC; Rd, Rn, RmSP

SMUAD

Thumb syntax (32-bit, v6T2)

SMUAD Rd, Rn, Rm [1]

Arm syntax (v6T2)

SMUAD Rd, Rn, Rm [1]

Notes

[1] Rd, Rn, RmPC; Rd, Rn, RmSP

SMUADX

Thumb syntax (32-bit, v6T2)

SMUADX Rd, Rn, Rm [1]

Arm syntax (v6T2)

SMUADX Rd, Rn, Rm [1]

Notes

[1] Rd, Rn, RmPC; Rd, Rn, RmSP

SMULBB

Description

Signed halfword multiply

Thumb syntax (32-bit, v6T2)

SMULBB Rd, Rn, Rm [1]

Arm syntax (v)

SMULBB Rd, Rn, Rm [1]

Notes

[1] Rd, Rn, RmPC; Rd, Rn, RmSP

SMULBT

Description

Signed halfword multiply

Thumb syntax (32-bit, v6T2)

SMULBT Rd, Rn, Rm [1]

Arm syntax (v6T2)

SMULBT Rd, Rn, Rm [1]

Notes

[1] Rd, Rn, RmPC; Rd, Rn, RmSP

SMULL

Thumb syntax (32-bit, v6T2)

SMULL Rd, Rn, Rm, Ra [1]

Arm syntax (v4T)

SMULL Rd, Rn, Rm, Ra [2]
SMULLS Rd, Rn, Rm, Ra [2]

Notes

[1] Rd, Rn, Rm, RaPC; Rd, Rn, Rm, RaSP; RdRn
[2] Rd, Rn, Rm, RaPC; RdRnRm

SMULTB

Description

Signed halfword multiply

Thumb syntax (32-bit, v6T2)

SMULTB Rd, Rn, Rm [1]

Arm syntax (v6T2)

SMULTB Rd, Rn, Rm [1]

Notes

[1] Rd, Rn, RmPC; Rd, Rn, RmSP

SMULTT

Description

Signed halfword multiply

Thumb syntax (32-bit, v6T2)

SMULTT Rd, Rn, Rm [1]

Arm syntax (v6T2)

SMULTT Rd, Rn, Rm [1]

Notes

[1] Rd, Rn, RmPC; Rd, Rn, RmSP

SMULWB

Description

Signed multiply wide

Thumb syntax (32-bit, v6T2)

SMULWB Rd, Rn, Rm [1]

Arm syntax (v)

SMULWB Rd, Rn, Rm [1]

Notes

[1] Rd, Rn, RmPC; Rd, Rn, RmSP

SMULWT

Description

Signed multiply wide

Thumb syntax (32-bit, v6T2)

SMULWT Rd, Rn, Rm [1]

Arm syntax (v)

SMULWT Rd, Rn, Rm [1]

Notes

[1] Rd, Rn, RmPC; Rd, Rn, RmSP

SMUSD

Thumb syntax (32-bit, v6T2)

SMUSD Rd, Rn, Rm [1]

Arm syntax (v6T2)

SMUSD Rd, Rn, Rm [1]

Notes

[1] Rd, Rn, RmPC; Rd, Rn, RmSP

SMUSDX

Thumb syntax (32-bit, v6T2)

SMUSDX Rd, Rn, Rm [1]

Arm syntax (v6T2)

SMUSDX Rd, Rn, Rm [1]

Notes

[1] Rd, Rn, RmPC; Rd, Rn, RmSP

SRS

Description

Store return state

Thumb syntax (32-bit, v6)

SRS SP, #031
SRS SP!, #031

Arm syntax (v6)

SRS SP, #031
SRS SP!, #031

SRSDA

Description

Store return state, decrement after

Arm syntax (v6)

SRSDA SP, #031
SRSDA SP!, #031

SRSDB

Description

Store return state, decrement before

Thumb syntax (32-bit, v6)

SRSDB SP, #031
SRSDB SP!, #031

Arm syntax (v6)

SRSDB SP, #031
SRSDB SP!, #031

SRSIA

Description

Store return state, increment after

Thumb syntax (32-bit, v6)

SRSIA SP, #031
SRSIA SP!, #031

Arm syntax (v6)

SRSIA SP, #031
SRSIA SP!, #031

SRSIB

Description

Store return state, increment before

Arm syntax (v6)

SRSIB SP, #031
SRSIB SP!, #031

SSAT

Description

Signed saturate

Thumb syntax (32-bit, v6T2)

SSAT Rd, #132, Rn [1]

Arm syntax (v6T2)

SSAT Rd, #132, Rn [1]

Notes

[1] Rd, RmPC; Rd, RmSP

SSAT16

Description

Signed saturate, parallel halfwords

Thumb syntax (32-bit, v6T2)

SSAT16 Rd, #116, Rn [1]

Arm syntax (v6T2)

SSAT16 Rd, #116, Rn [1]

Notes

[1] Rd, RmPC; Rd, RmSP

SSAX

Thumb syntax (32-bit, v6T2)

SSAX Rd, Rn, Rm [1]

Arm syntax (v6T2)

SSAX Rd, Rn, Rm [1]

Notes

[1] Rd, Rn, RmPC; Rd, Rn, RmSP

SSUB16

Thumb syntax (32-bit, v6T2)

SSUB16 Rd, Rn, Rm [1]

Arm syntax (v6T2)

SSUB16 Rd, Rn, Rm [1]

Notes

[1] Rd, Rn, RmPC; Rd, Rn, RmSP

SSUB8

Thumb syntax (32-bit, v6T2)

SSUB8 Rd, Rn, Rm [1]

Arm syntax (v6T2)

SSUB8 Rd, Rn, Rm [1]

Notes

[1] Rd, Rn, RmPC; Rd, Rn, RmSP

STL

Description

Store-release word

Thumb syntax (32-bit, v)

STL Rd, [Rn] [1]

Arm syntax (v)

STL Rd, [Rn] [1]

Notes

[1] Rd, RnPC; RdSP

STLB

Description

Store-release byte

Thumb syntax (32-bit, v)

STLB Rd, [Rn] [1]

Arm syntax (v)

STLB Rd, [Rn] [1]

Notes

[1] Rd, RnPC; RdSP

STLH

Description

Store-release halfword

Thumb syntax (32-bit, v)

STLH Rd, [Rn] [1]

Arm syntax (v)

STLH Rd, [Rn] [1]

Notes

[1] Rd, RnPC; RdSP

STM

Description

Store multiple

Thumb syntax (16-bit, v4T)

STM Rd, {Rn, Rm}
STM Rd!, {Rn, Rm} [1]

Thumb syntax (32-bit, v6T2)

STM Rd, {Rn, Rm} [2]
STM Rd!, {Rn, Rm} [2]

Arm syntax (v4T)

STM Rd, {Rn, Rm} [2]
STM Rd!, {Rn, Rm} [2]

Notes

[1] Rd must be R0R7; RdPC
[2] RdPC

STMDA

Description

Store multiple decrement after

Thumb syntax (16-bit, v4T)

STMDA Rd, {Rn, Rm}

Thumb syntax (32-bit, v6T2)

STMDA Rd, {Rn, Rm} [1]
STMDA Rd!, {Rn, Rm} [1]

Arm syntax (v4T)

STMDA Rd, {Rn, Rm} [1]
STMDA Rd!, {Rn, Rm} [1]

Notes

[1] RdPC

STMDB

Description

Store multiple decrement before

Thumb syntax (16-bit, v4T)

STMDB SP!, {Rn, Rm}

Thumb syntax (32-bit, v6T2)

STMDB Rd, {Rn, Rm} [1]
STMDB Rd!, {Rn, Rm} [1]

Arm syntax (v4T)

STMDB Rd, {Rn, Rm} [1]
STMDB Rd!, {Rn, Rm} [1]

Notes

[1] RdPC

STMEA

Description

Store multiple empty ascending

Thumb syntax (16-bit, v4T)

STMEA SP!, {Rn, Rm}

Thumb syntax (32-bit, v6T2)

STMEA Rd, {Rn, Rm} [1]
STMEA Rd!, {Rn, Rm} [1]

Arm syntax (v4T)

STMEA Rd, {Rn, Rm} [1]
STMEA Rd!, {Rn, Rm} [1]

Notes

[1] RdPC

STMED

Description

Store multiple empty descending

Thumb syntax (16-bit, v4T)

STMED Rd, {Rn, Rm}

Thumb syntax (32-bit, v6T2)

STMED Rd, {Rn, Rm} [1]
STMED Rd!, {Rn, Rm} [1]

Arm syntax (v4T)

STMED Rd, {Rn, Rm} [1]
STMED Rd!, {Rn, Rm} [1]

Notes

[1] RdPC

STMFA

Description

Store multiple full ascending

Thumb syntax (16-bit, v4T)

STMFA Rd, {Rn, Rm}

Thumb syntax (32-bit, v6T2)

STMFA Rd, {Rn, Rm} [1]
STMFA Rd!, {Rn, Rm} [1]

Arm syntax (v4T)

STMFA Rd, {Rn, Rm} [1]
STMFA Rd!, {Rn, Rm} [1]

Notes

[1] RdPC

STMFD

Description

Store multiple full descending

Thumb syntax (16-bit, v4T)

STMFD Rd, {Rn, Rm}
STMFD Rd!, {Rn, Rm} [1]

Thumb syntax (32-bit, v6T2)

STMFD Rd, {Rn, Rm} [2]
STMFD Rd!, {Rn, Rm} [2]

Arm syntax (v4T)

STMFD Rd, {Rn, Rm} [2]
STMFD Rd!, {Rn, Rm} [2]

Notes

[1] Rd must be R0R7; RdPC
[2] RdPC

STMIA

Description

Store multiple increment after

Thumb syntax (16-bit, v4T)

STMIA Rd, {Rn, Rm}
STMIA Rd!, {Rn, Rm} [1]

Thumb syntax (32-bit, v6T2)

STMIA Rd, {Rn, Rm} [2]
STMIA Rd!, {Rn, Rm} [2]

Arm syntax (v4T)

STMIA Rd, {Rn, Rm} [2]
STMIA Rd!, {Rn, Rm} [2]

Notes

[1] Rd must be R0R7; RdPC
[2] RdPC

STMIB

Description

Store multiple increment before

Thumb syntax (16-bit, v4T)

STMIB Rd, {Rn, Rm}

Thumb syntax (32-bit, v6T2)

STMIB Rd, {Rn, Rm} [1]
STMIB Rd!, {Rn, Rm} [1]

Arm syntax (v4T)

STMIB Rd, {Rn, Rm} [1]
STMIB Rd!, {Rn, Rm} [1]

Notes

[1] RdPC

STR

Description

Store word

Thumb syntax (16-bit, v4T)

STR Rt, [Rn, #0124] [1]
STR Rt, [SP, #01020] [2]
STR Rt, [Rn, Rm] [3]

Thumb syntax (32-bit, v6T2)

STR Rt, [Rn, #2554095] [4]
STR Rt, [Rn, #255255]! [5]
STR Rt, [Rn], #255255 [5]
STR Rt, [Rn, Rm, LSL #13] [6]

Arm syntax (v4T)

STR Rt, [Rn, #40954095] [5]
STR Rt, [Rn, #40954095]! [5]
STR Rt, [Rn], #40954095 [5]
STR Rt, [Rn], ±Rm, shift [7]
STR Rt, [Rn, ±Rm] [7]
STR Rt, [Rn, ±Rm]! [7]

Notes

[1] Rt, Rn must be R0R7; offset a multiple of 4
[2] offset a multiple of 4
[3] Rt, Rn, Rm must be R0R7
[4] Rt, RnPC
[5] Rt, RnPC; RtRn
[6] Rt, Rn, RmPC; RmSP; LSL #0 is also permitted
[7] Rt, Rn, RmPC; RmSP; RtRn

STRB

Description

Store byte

Thumb syntax (16-bit, v4T)

STRB Rt, [Rn, #031] [1]
STRB Rt, [Rn, Rm] [2]

Thumb syntax (32-bit, v6T2)

STRB Rt, [Rn, #2554095] [3]
STRB Rt, [Rn, #255255]! [4]
STRB Rt, [Rn], #255255 [4]
STRB Rt, [Rn, Rm, LSL #13] [5]

Arm syntax (v4T)

STRB Rt, [Rn, #40954095] [3]
STRB Rt, [Rn, #40954095]! [4]
STRB Rt, [Rn], #40954095 [4]
STRB Rt, [Rn], ±Rm, shift [6]
STRB Rt, [Rn, ±Rm] [7]
STRB Rt, [Rn, ±Rm]! [6]

Notes

[1] Rt, Rn must be R0R7
[2] Rt, Rn, Rm must be R0R7
[3] Rt, RnPC; RtSP
[4] Rt, RnPC; RtSP; RtRn
[5] Rt, Rn, RmPC; Rt, RmSP; LSL #0 is also permitted
[6] Rt, Rn, RmPC; Rt, RmSP; RtRn
[7] Rt, Rn, RmPC; Rt, RmSP

STRBT

Description

Store byte, user mode

Thumb syntax (32-bit, v6T2)

STRBT Rt, [Rn, #0255] [1]

Arm syntax (v4T)

STRBT Rt, [Rn], #40954095 [2]
STRBT Rt, [Rn], ±Rm, shift [3]

Notes

[1] Rt, RnPC; RtSP
[2] Rt, RnPC; RtSP; RtRn
[3] Rt, Rn, RmPC; Rt, RmSP; RtRn

STRD

Description

Store doubleword

Thumb syntax (32-bit, v6T2)

STRD Rd1, Rd2, [Rn, #10201020] [1]
STRD Rd1