Olimex LPC-2478STK

Controller:
  • LPC2478FET208 (NXP)
CPU:
  • ARM7TDMI-S
Board main features:
  • NXP LPC2478 (ARM7TDMI-S) microcontroller in BGA package
  • 512 kB internal flash
  • 64 MB external SDRAM
  • 96 KB internal RAM
  • MP3 decoder DSP + codec VS1002
  • 3-axis digital accelerometer with 11-bit accuracy
  • IrDA transceiver
  • PS/2 keyboard connector
  • RS232 with ICSP control
  • Reset button and circuit
  • 2 buttons
  • 1 trimpod
  • UEXT connector
  • Audio IN
  • Audio OUT
  • RTC battery
  • FR-4, 1.5 mm, red soldermask, component pin
  • 100/10 MBit Ethernet interface
  • 12.000 MHz crystal for CPU
  • 3.5 inch QVGA TFT color LCD with touch screen panel
  • Ethernet connector (RJ45)
  • MMC/SD interface & connector
  • CAN interface & connector
  • JTAG connector
  • ETM connector
  • USB device interface & connector
  • USB host interface & connector
  • Power supply, either via J-Link or external 9-12V DC
Controller main features:
  • ARM7TDMI-S processor, running at up to 72 MHz.
  • 512 kB on-chip flash program memory with In-System Programming (ISP) and In-Application Programming (IAP) capabilities. Flash program memory is on the ARM local bus for high performance CPU access.
  • 98 kB on-chip SRAM includes:
    • 64 kB of SRAM on the ARM local bus for high performance CPU access.
    • 16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.
    • 16 kB SRAM for general purpose DMA use also accessible by the USB.
    • 2 kB SRAM data storage powered from the RTC power domain.
  • LCD controller, supporting both Super-Twisted Nematic (STN) and Thin-Film Transistors (TFT) displays.
    • Dedicated DMA controller.
    • Selectable display resolution (up to 1024 × 768 pixels).
    • Supports up to 24-bit true-color mode.
  • Dual Advanced High-performance Bus (AHB) system allows simultaneous Ethernet DMA, USB DMA, and program execution from on-chip flash with no contention.
  • EMC provides support for asynchronous static memory devices such as RAM, ROM and flash, as well as dynamic memories such as Single Data Rate SDRAM.
  • Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.
  • General Purpose AHB DMA controller (GPDMA) that can be used with the SSP, I2S, and SD/MM interface as well as for memory-to-memory transfers.
  • Serial Interfaces:
    • Ethernet MAC with MII/RMII interface and associated DMA controller. These functions reside on an independent AHB bus.
    • USB 2.0 full-speed dual-port device/host/OTG controller with on-chip PHY and associated DMA controller.
    • Four UARTs with fractional baud rate generation, one with modem control I/O, one with IrDA support, all with FIFO.
    • CAN controller with two channels.
    • SPI controller.
    • Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate for the SPI port, sharing its interrupt. SSPs can be used with the GPDMA controller.
    • Three I2C-bus interfaces (one with open-drain and two with standard port pins).
    • I2S (Inter-IC Sound) interface for digital audio input or output. It can be used with the GPDMA.
  • Other peripherals:
    • SD/MMC memory card interface.
    • 160 General purpose I/O pins with configurable pull-up/down resistors.
    • 10-bit ADC with input multiplexing among 8 pins.
    • 10-bit DAC.
    • Four general purpose timers/counters with 8 capture inputs and 10 compare outputs. Each timer block has an external count input.
    • Two PWM/timer blocks with support for three-phase motor control. Each PWM has an external count inputs.
    • Real-Time Clock (RTC) with separate power domain. Clock source can be the RTC oscillator or the APB clock.
    • 2 kB SRAM powered from the RTC power pin, allowing data to be stored when the rest of the chip is powered off.
    • WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the RTC oscillator, or the APB clock.
  • Single 3.3 V power supply (3.0 V to 3.6 V).
  • 4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as the system clock.
  • Three reduced power modes: idle, sleep, and power-down.
  • Four external interrupt inputs configurable as edge/level sensitive. All pins on PORT0 and PORT2 can be used as edge sensitive interrupt sources.
  • Processor wake-up from Power-down mode via any interrupt able to operate during Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet wake-up interrupt, CAN bus activity, PORT0/2 pin interrupt).
  • Two independent power domains allow fine tuning of power consumption based on needed features.
  • Each peripheral has its own clock divider for further power saving. These dividers help reducing active power by 20 - 30 %.
  • Brownout detect with separate thresholds for interrupt and forced reset.
  • On-chip power-on reset.
  • On-chip crystal oscillator with an operating range of 1 MHz to 24 MHz.
  • On-chip PLL allows CPU operation up to the maximum CPU rate without the need for a high frequency crystal. May be run from the main oscillator, the internal RC oscillator, or the RTC oscillator.
  • Boundary scan for simplified board testing.
  • Versatile pin function selections allow more possibilities for using on-chip peripheral functions.
  • Standard ARM test/debug interface for compatibility with existing tools.
  • Emulation trace module supports real-time trace.
Available software:
Available documentation: