GUIDRV_Page1bpp
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emWin driver GUIDRV_Page1bpp
Supported hardware
Controllers
This driver works with the following display controllers:
- Epson S1D10605, S1D15605, S1D15705, S1D15710, S1D15714, S1D15721
- Epson S1D15E05, S1D15E06, SED1520, SED1560, SED1565, SED1566
- Epson SED1567, SED1568, SED1569, SED1575
- Hitachi HD61202
- IST IST3020
- New Japan Radio Company NJU6676, NJU6679
- Novatek NT7502, NT7534, NT7538, NT75451
- Philips PCF8810, PCF8811, PCF8535, PCD8544
- Samsung KS0108B, KS0713, KS0724
- Samsung S6B0108B, S6B0713, S6B0719, S6B0724, S6B1713
- Sino Wealth SH1101A
- Sitronix ST7522, ST7565, ST7567
- Solomon SSD1303, SSD1805, SSD1815
- ST Microelectronics ST7548, STE2001, STE2002
- Sunplus SPLC501C
- UltraChip UC1601, UC1606, UC1608, UC1701
It should be assumed that it will also work with any controller of similar organization
Bits per pixel
Supported color depth is 1bpp.
Interfaces
The driver supports the indirect interface (8 bit) of the display controller. Parallel, 4-pin SPI or I2C bus can be used.
Available configuration macros (compile time configuration)
Controller selection
The following table shows the available macro:
| Macro | Description |
|---|---|
| LCD_CONTROLLER | Selects the display controller to be used: 1501 - Samsung KS0713, KS0724, S6B0713, S6B0724 1501 - UltraChip UC1601, UC1606 1502 - Samsung KS0108B S6B0108B 1503 - Hitachi HD61202 1504 - Philips PCF8810, PCF8811 1505 - Philips PCF8535 1506 - New Japan Radio Company NJU6679 1507 - Philips PCD8544 1508 - Epson S1D15710 1509 - Solomon SSD1303 OLED controller 1510 - Epson S1D15714 1510 - IST 3020 1510 - New Japan Radio Company NJU6676 1510 - Novatek NT7538, NT75451 1510 - Samsung S6B0719 1510 - Sino Wealth SH1101A 1510 - Sitronix ST7522, ST7565, ST7567 1510 - Solomon SSD1805 1510 - UltraChip UC1608, UC1701 1511 - Epson S1D15721 1512 - Epson S1D15E05, S1D15E06 1513 - ST Microelectronics ST7548, STE2001, STE2002 1520 - Epson SED1520 1560 - Epson SED1560 1565 - Epson SED1565, S1D10605, S1D15605 1565 - Novatek NT7502, NT7534 1565 - Samsung S6B1713 1565 - Solomon SSD1815 1565 - Sunplus SPLC501C 1566 - Epson SED1566 1567 - Epson SED1567 1568 - Epson SED1568 1569 - Epson SED1569 1575 - Epson SED1575, S1D15705 |
Display data RAM organization
The picture above shows the relation between the display memory and the SEG and COM lines of the LCD.
Additional RAM requirements of the driver
This LCD driver can be used with or without a display data cache in the most cases. If one display contains more
than 1 LCD controller you can not disable the cache. The data cache contains a complete copy of the contents of
the LCD data RAM. If a cache is not used, there are no additional RAM requirements. It is recommended to use this
driver with a data cache for faster LCD-access. The amount of memory used by the cache may be calculated as follows:
Size of RAM (in bytes) = (LCD_YSIZE + 7) / 8 * LCD_XSIZE
Additional driver functions
LCD_L0_ControlCache
For information about this function, please refer to the end of this chapter.
Hardware configuration
This driver accesses the hardware with the indirect interface. The following table lists the macros which must be
defined for hardware access:
| Macro | Explanation |
|---|---|
| LCD_READ_A0 | Read a byte from LCD controller with A-line low. |
| LCD_READ_A1 | Read a byte from LCD controller with A-line high. |
| LCD_WRITE_A0 | Write a byte to LCD controller with A-line low. |
| LCD_WRITE_A1 | Write a byte to LCD controller with A-line high. |
| LCD_WRITEM_A1 | Write multiple bytes to LCD controller with A-line high. |
Display orientation
Some of the supported display controllers supports hardware mirroring of x/y axis. It is reccomended to use these
functions instead of the display orientation macros of emWin.
If mirroring of the X axis is needed, the command 0xA1 (ADC select reverse) should be used in the initialization macro.
This causes the display controller to reverse the assignment of column address to segment output. If the display size
in X is smaller than the number of segment outputs of the display controller, the macro LCD_FIRSTSEG0 can be used
to add an offset to the column address to make sure, the right RAM address of the LCD controller is accessed.
If mirroring of the Y axis is needed the command 0xC8 (SHL select revers) should be used in the initialization macro
and the macro LCD_FIRSTCOM0 should be used to define the offset needed to access the right RAM address of the
display controller.
Additional configuration switches
The following table shows optional configuration switches available for this driver:
| Macro | Explanation |
|---|---|
| LCD_CACHE | When set to 0, no display data cache is used, which slows down the speed of the driver. Default is 1 (cache activated). |
| LCD_FIRSTCOM0 | This macro can be used to define the first common address to be used in the data RAM of the display controller. The value can be determined experimentally or taken from the display doc. |
| LCD_FIRSTSEG0 | This macro can be used to define the first segment address to be used in the data RAM of the display controller. The value can be determined experimentally or taken from the display doc. |
| LCD_SUPPORT_CACHECONTROL | When set to 1, the cache control functions of LCD_L0_ControlCache() driver API are enabled. |
Special requirements for certain LCD controllers
None.
