Readme.txt for sample project for CPU V850E2S_FG4

This project was built for the IAR Workbench for V850 V3.81.1

It has been tested with version V3.81.1


Supported hardware:
===================
The sample project is prepared
to run on an Y-ASK-V850ES-FG4 starterkit.
or can be used with the CSpy simulator.

Using different hardware or device may
require modifications.

Configurations
==============
- DEBUG_DP:
  This configuration is prepared for download into
  the target CPU using the Renesas R1 debugger probe and CSpy.
  An embOS debug and profiling library is used.

- TARGET_SP:
  This configuration is prepared for download into
  the target CPU using the Renesas R1 debugger probe and CSpy.
  It uses an embOS stack check an profiling library.

- SIM_DP:
  This configuration is prepared to be used
  with the CSpy simulator.
  The embOS timer interrupt is simulated by a CSpy macro file.
  An embOS debug and profiling library is used.
