ReadMe.txt for the Freedom E31 Coreplex IP start project.

This project was built for SEGGER Embedded Studio for RISC-V V6.30.

Supported hardware:
===================
The sample project for the Freedom E31 Coreplex IP is prepared to
run on a Digilent Arty FPGA Dev Kit. Using different target hardware
may require modifications.

Configurations:
===============
- Debug:
  This configuration is prepared for download into internal
  Flash using J-Link. An embOS debug and profiling library
  is used.
  To use SEGGER SystemView with this configuration, configure
  SystemView for E31ARTY as target device and JTAG at 2000 kHz
  as target interface.

- Release:
  This configuration is prepared for download into internal
  Flash using J-Link. An embOS release library is used.
