ReadMe.txt for the Xilinx XCZU3EG (Cortex-A53_0) start project.

This project was built for Xilinx SDK V2018.3 and consists of three distinct parts:
- hw_platform_0:              Contains the examplary Zynq UltraScale+ Design used as basis for the below application and BSP projects.
- Start_XCZU3EG_A53_0:        Contains the application project (including embOS) based on the referenced Zynq UltraScale+ design.
- Start_XCZU3EG_A53_0_LibXil: Contains the generated board support package (Xilinx driver library) for the referenced the Zynq UltraScale+ design.

To utilize these, import all three into Elipse / Xilinx SDK simultaneously, then build the application project and use it for further development.

Supported hardware:
===================
The sample project for the Xilinx XCZU3EG (Cortex-A53_0) is prepared to
run on an Avnet Ultra96 board. Using different target hardware may
require modifications.

Configurations:
===============
- Debug:
  This configuration is prepared for download into internal RAM using an
  Ultra96 USB-to-JTAG/UART Pod. An embOS debug and profiling library
  is used.

- Release:
  This configuration is prepared for download into internal RAM using an
  Ultra96 USB-to-JTAG/UART Pod. An embOS release library is used.
