The clocked synchronus interface from Flasher to target
system is realized by a 10 pin dual in line pin connector, (pin1 is marked
at the connector) at the front of FLASHER. Function depends on selected
target.
| 1 |
VCCS |
Positive supply voltage of target |
Input 3.0..5.5V to supply the interface |
| 2 |
RCLK |
Target CPU return clock signal |
FLASHER Input with Pull-Up to VCCS |
| 3 |
SCLK |
Target CPU serial clock (input) |
FLASHER Output, CMOS driver via 220 Ohms |
| 4 |
RxD |
Target CPU serial data input |
FLASHER Output, CMOS driver via 220 Ohms |
| 5 |
Test |
Enable signal for target CPU |
FLASHER Output, CMOS driver via 220 Ohms |
| 6 |
Boot |
Enable signal for target CPU |
FLASHER Output, CMOS driver via 220 Ohms |
| 7 |
GND |
Common signal ground |
--- |
| 8 |
RESET |
RESET signal for target system |
FLASHER Output, CMOS driver via 220 Ohms |
| 9 |
Boot2 |
Enable signal for target CPU |
FLASHER Output, 2.2KOhm pull down |
| 10 |
TxD |
Target CPU Serial data output |
FLASHER Input with Pull-up to VCCS |
If RESET of target system is driven by a reset circuitry
with active high driver, RESET output of FLASHER must not be connected
directly to CPU reset of target
| Pin |
Function |
Pin |
Port |
Pin |
Port |
Pin |
Port |
| 1 |
VCCS: Target supply voltage |
5 |
(VDD) |
5 |
(VDD) |
5 |
8VDD) |
| 2 |
RCLK: Return clock from target CPU |
15 |
P04 |
22 |
P14 |
24 |
P14 |
| 3 |
SCLK: Serial clock to target CPU |
18 |
P07 |
19 |
P17 |
27 |
P17 |
| 4 |
RxD: Serial data to target CPU |
16 |
P05 |
21 |
P15 |
25 |
P15 |
| 5 |
Test: Boot mode enable signal |
4 |
(TEST) |
4 |
(TEST) |
4 |
(TEST) |
| 6 |
Boot: Boot mode enable signal |
10 |
(BOOT) |
nc |
--- |
nc |
--- |
| 7 |
GND: Common ground |
1 |
(VSS) |
1 |
(VSS) |
1 |
(VSS) |
| 8 |
RESET: Reset to target CPU |
8 |
(RESET) |
8 |
(RESET) |
8 |
(RESET) |
| 9 |
Boot2: Boot mode enable signal |
68 |
P11 |
25 |
P11 |
21 |
P11 |
| 10 |
TxD: Serial data from target CPU |
17 |
P06 |
20 |
P16 |
26 |
P16 |
| Pin |
Function |
Pin |
Port |
| 1 |
VCCS: Target supply voltage |
18 |
(DVCC) |
| 2 |
RCLK: Return clock from target CPU |
13 |
P92 |
| 3 |
SCLK: Serial clock to target CPU |
16 |
P95 |
| 4 |
RxD: Serial data to target CPU |
15 |
P94 |
| 5 |
Test: Boot mode enable signal |
4nc |
--- |
| 6 |
Boot: Boot mode enable signal |
50 |
(BOOT) |
| 7 |
GND: Common ground |
20 |
(DVSS) |
| 8 |
RESET: Reset to target CPU |
23 |
(RESET) |
| 9 |
Boot2: Boot mode enable signal |
nc |
--- |
| 10 |
TxD: Serial data from target CPU |
14 |
P93 |
Flasher 5T: Target interface
for TLCS_870/C and TMP91 CPUs
