Using the CPU as LCD controller

In systems with relatively fast CPUs and small (quarter VGA or less) LCDs, there is no need for an LCD controller. The microcontroller (CPU) can do the job of the LCD controller on the side, refreshing the display in an interrupt service routine. The CPU™s memory is used as video memory.
Advantages of this approach include the following:

• Very fast update of display possible.
• Eliminating the LCD controller (and its external RAM) reduces hardware costs.
• Simplified hardware design.
• 2/4/16 levels of gray can be displayed.

The disadvantage is that much of the available computation time is used up. Depending on the CPU, this can be anything between 20 and almost 100 percent; with slower CPUs, it is really not possible at all.
This type of interface does not require a specific LCD driver because emWin simply places all the display data into the LCD cache. You yourself must write the hardware dependent portion that periodically transfers the data in the cache memory to your LCD. Sample code for transferring the video image into the display is available in both "C" and optimized assembler for M16C and M16C/80.

How to connect the CPU to the row/column drivers

It is quite easy to connect the microcontroller to the row/column drivers. Five control lines are needed, as well as either 4 or 8 data lines (depending on whether the column drivers are able to operate in 8-bit mode). 8-bit mode is recommended as it is more efficient, saving calculation time of the CPU. All data lines should be on a single port, using port bits 0..3 or 0..7 in order to guarantee efficient access. This setup is illustrated below:

CPU load

The CPU load depends on the hardware and controller used, as well as on the size of the display.
For example:
Renesas M16C62 Controller, 16MHz, 160*100 display, 8-bit interface, 80 Hz update
= app. 12% CPU load
Renesas M16C62 Controller, 16MHz, 240*128 display, 8-bit interface, 80 Hz update
= app. 22% CPU load

Supported hardware

Controllers

None.

Bits per pixel

Supported color depth is 2 bpp.

Interfaces

The driver supports 1/4/8-bit interfaces from the CPU to the LCD.

Display data RAM organization

The picture above shows the relation between the display memory and the SEG and COM lines of the LCD. The display memory is divided into two panes for each pixel. The lower bit of one pixel is stored in pane 0 and the higher bit is stored in pane 1. The advantage of this method is that the output of the display data can be executed very quickly.

Additional RAM requirements of the driver

The driver only handles a memory area containing the display data. The required size of the display memory area may be calculated as follows:
Size of RAM (in bytes) = (LCD_XSIZE + 7) / 8 * LCD_YSIZE * 2

Additional driver functions

None.

Hardware configuration

Normally, the hardware interface is an interrupt service routine (ISR) which updates the LCD. An output routine written in "C" code is shipped with emWin. This routine should serve only as an example. To optimize the execution speed, it must be adapted in assembler code.

Additional configuration switches

The following table shows optional configuration switches available for this driver: