emWin: LCDLin driver

This driver can be used with any LCD Controller with linear memory organization (as described below) and full bus interface. Most controllers for bigger displays and higher color depth (typically starting at quarter VGA) conform with this requirement and can therefore be controlled by this driver.

Supported hardware

Controllers

The following table list the supported controllers and their assigned numbers, as well as the level of support:

LCD_CONTROLLER	LCD controller	Add. info
1300	Any LCD controller with linear memory and full bus interface, such as: Epson SED1352, S1D13502 Epson SED1353, S1D13503 Epson S1D13700 (direct interface) Solomon SSD1905 Fujitsu MB86276 (Lime) Fujitsu MB86290A (Cremson) Fujitsu MB86291 (Scarlet) Fujitsu MB86292 (Orchid) Fujitsu MB86293 (Coral Q) Fujitsu MB86294 (Coral B) Fujitsu MB86295 (Coral P) Microcontroller with built-in LCD controllers such as Sharp LH79531	The LUT (color look up table) is not handled by the driver. If a LUT mode is used (typically 16 or 256 colors), the application program is responsible for initialization of the LUT.
1301	Toshiba Capricorn 2	LUT is handled by driver if required. All layers can be supported
1304	Epson S1D13A03, S1D13A04, S1D13A05	LUT is handled by driver if required 2 D Engine supported (BitBLT)
1354	Epson SED1354, S1D13504	LUT is handled by driver if required.
1356	Epson SED1356, S1D13506	LUT is handled by driver if required. 2D Engine supported (BitBLT)
1374	Epson SED1374, S1D13704	LUT is handled by driver if required.
1375	Epson SED1375, S1D13705	LUT is handled by driver if required.
1376	Epson SED1376, S1D13706	LUT is handled by driver if required.
1386	Epson SED1386, S1D13806	LUT is handled by driver if required. 2D Engine supported (BitBLT)

Bits per pixel

Supported color depths are 1, 2, 4, 8 and 16 bpp.

Interfaces

The chips supported by this driver can be interfaced in 8/16-bit parallel (full bus) modes.
The driver supports both interfaces. Please refer to the respective LCD controller manual in order to determine if your chip can be interfaced in 8-bit mode.

Built-in LCD controllers

This driver can also be used with built-in LCD controllers. In this case, either 8 or 16 bit access can be selected. It is typically best to use 8 bit access if the built-in LCD controller operates in an 8-bpp mode and likewise to use 16 bit access if the built-in LCD-controller operates in a 16-bpp mode.

Interfaces

Built-in LCD controllers

Display data RAM organization

The picture above shows the relation between the display memory and the SEG and COM lines of the LCD in terms of the color depth.

Additional RAM requirements of the driver

None.

Additional driver functions

None.

Hardware configuration

This driver requires a full bus interface for hardware access. The following table lists the macros which must be defined for hardware access:

Macro	Explanation
LCD_INIT_CONTROLLER	Initialization sequence for the LCD controller.
LCD_READ_MEM	Read the contents of video memory of controller.
LCD_READ_REG	Read the contents of a register of controller.
LCD_WRITE_MEM	Write to video memory (display data RAM) of controller.
LCD_WRITE_REG	Write to configuration registers of controller.

Additional configuration switches

The following table shows optional configuration switches available for this driver:

Macro	Explanation
LCD_BUS_WIDTH	Select bus-width (8/16) of LCD controller/CPU interface. Default is 16.
LCD_CNF4	Endian mode selection for S1D13A03-A05 controllers. Default is 0.
LCD_ENABLE_MEM_ACCESS	Switch the M/R signal to memory access. Only used for SED1356 and SED1386 LCD controllers.
LCD_ENABLE_REG_ACCESS	Switch the M/R signal to register access. Only used for SED1356 and SED1386 LCD controllers.
LCD_FILL_RECT	LCD_FILL_RECT Function replacement macro which defines a function to be called by the driver for filling rectangles. For details please refer to LCDLin-driver (32 bit access).
LCD_ON	Function replacement macro which switches the LCD on.
LCD_OFF	Function replacement macro which switches the LCD off.
LCD_SET_LUT_ENTRY	Function replacement macro used to set a single lookup table or palette RAM entry.
LCD_SWAP_BYTE_ORDER	Inverts the endian mode (swaps the high and low bytes) between CPU and LCD controller when using a 16-bit bus-interface.
LCD_USE_BITBLT	If set to 0, it disables the BitBLT engine. If set to 1 (the default value), the driver will use all available hardware acceleration.

Special requirements for certain LCD controllers

SED1386 or S1D13806

LCD_SWAP_RB
The configuration switch LCD_SWAP_RBLCD_SWAP_RB (swaps the red and blue components) must be activated (set to 1) by inserting the following line into LCDConf.h:
#define LCD_SWAP_RB (1) /* Has to be set */

LCD_INIT_CONTROLLER
When writing or modifying the initialization macro, consider the following:

To initialize the embedded SDRAM, bit 7 of register 20 (SDRAM initialization bit) must be set to 1 (a minimum of 200 µs after reset).
When the SDRAM initialization bit is set, the actual initialization sequence occurs at the first SDRAM refresh cycle. The initialization sequence requires approximately 16 MCLKs to complete, and memory accesses cannot be made while the initialization is in progress.

For more information, please see the LCD controller documentation.

LCD_READ_REG, LCD_WRITE_REG
In order for the BitBLT-engine to work, the data type of the offset must be unsigned long. This is set with the configuration macros LCD_READ_REG and LCD_WRITE_REG as follows:
#define LCD_READ_REG(Off)*((volatile U16*)(0x800000+(((U32)(Off))<<1)))
#define LCD_WRITE_REG(Off,Data) *((volatile U16*)(0x800000+(((U32)(Off))<<1)))=Data