Supported hardware
Controllers
This driver has been tested with the following LCD controllers
It should be assumed that it will also work with any
controller of similar organization.
Bits per pixel
Supported color depth is 2 bpp.
Interfaces
Both 8-bit parallel (simple bus) interfaces and serial
(SPI) interfaces are supported.
Display data RAM organization
The picture above shows the relation between the display
memory and the SEG and COM lines of the LCD.
Additional RAM requirements of the driver
This LCD driver may be used with or without a display
data cache, containing a complete copy of the contents of the LCD data
RAM. If a cache is not used, there are no additional RAM requirements.
It is recommended to use this driver with a data cache
for faster LCD-access. The amount of memory used by the cache may be calculated
as follows:
Size of RAM (in bytes) = (LCD_YSIZE + 7) / 8 * LCD_XSIZE
Additional driver functions
None.
Hardware configuration
This driver accesses the hardware with a simple bus
interface. The following table lists the macros which must be defined
for hardware access:
| LCD_INIT_CONTROLLER |
Initialization sequence for the LCD controller. |
| LCD_READ_A0 |
Read a byte from LCD controller with A-line low. |
| LCD_READ_A1 |
Read a byte from LCD controller with A-line high. |
| LCD_WRITE_A0 |
Write a byte to LCD controller with A-line low. |
| LCD_WRITE_A1 |
Write a byte to LCD controller with A-line high. |
Additional configuration switches
The following table shows optional configuration switches
available for this driver:
| LCD_CACHE |
Activate display cache. When set to 0, no data cache is used. Using
the driver without cache slows down the speed of the driver. |
Special requirements for certain LCD controllers
None.

Copyright SEGGER Microcontroller GmbH & Co.KG.
All rights reserved.
For more information, please visit our web site
www.segger.com or contact us at info@segger.com
Last update:
December 7, 2007
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