emWin: LCDPage4bpp driver

Supported hardware

Controllers

This driver has been tested with the following LCD controllers

Sitronix ST7528

Bits per pixel

Supported color depth is 4 bpp.

Interfaces

The driver supports 8-bit parallel (simple bus) and 4 pin SPI interface.

Display data RAM organization

The picture above shows the relation between the display memory and the SEG and COM lines of the LCD. The display memory is divided into four panes for each pixel. The least significant bit (LSB) of each pixel is stored in pane 0 and the MSB is stored in pane 3.

Additional RAM requirements of the driver

This LCD driver may be used with or without a display data cache. If the cache is used it holds a complete copy of the contents of the LCD data RAM. If cache is not used, there are no additional RAM requirements.
It is recommended to use this driver with a data cache for faster LCD-access. The amount of memory used by the cache may be calculated as follows:
Size of RAM (in bytes) = (LCD_YSIZE + 7) / 8 * LCD_XSIZE * 4. A cache is required in SPI mode, because SPI does not allow reading of display con- tents.

Additional driver functions

None

Hardware configuration

This driver accesses the hardware with a simple bus interface, a 4 pin SPI interface or a I2C bus interface as described in Chapter 26: "Low-Level Configuration". The following table lists the macros which must be defined for hardware access:

Macro	Explanation
LCD_INIT_CONTROLLER	Initialization sequence for the LCD controller.
LCD_READ_A1	Read a byte from LCD controller with A-line high.(Used only if working without cache)
LCD_WRITE_A0	Write a byte to LCD controller with A-line low.
LCD_WRITE_A1	Write a byte to LCD controller with A-line high.
LCD_WRITEM_A1	Write multiple bytes to LCD controller with A-line high.

Display Orientation

A Sitronix ST7528 display controller supports hardware mirroring of x/y axis. It is reccomended to use these functions instead of the display orientation macros of emWin. If mirroring of the X axis is needed, the command 0xA1 (ADC select reverse) should be used in the initialization macro. This causes the display controller to reverse the assignment of column address to segment output. If the display size in X is smaller than the number of segment outputs of the display controller, the macro LCD_FIRSTSEG0 can be used to add an offset to the column address to make sure, the right RAM address of the LCD controller is accessed. If mirroring of the Y axis is needed the command 0xC8 (SHL select revers) should be used in the initialization macro and the macro LCD_FIRSTCOM0 should be used to define the offset needed to access the right RAM address of the display controller.

Additional configuration switches

The following table shows optional configuration switches available for this driver:

Macro	Explanation
LCD_FIRSTCOM0	This macro can be used to define the first common address to be used in the data RAM of the display controller. The value can be determined experimentally or taken from the display documentation.
LCD_FIRSTSEG0	This macro can be used to define the first segment address to be used in the data RAM of the display controller. The value can be determined experimentally or taken from the display documentation.
LCD_NUM_COM0	A Sitronix ST7528 controller can operate in 2 modes. Mode 0 with 132 segment and 128 common outputs and mode 1 with 160 segment and 100 common outputs. which mode is used depends on hardware, the mode can not be changed via command. Defines the number of available common outputs of the display controller. Possible values for Sitronix ST7528 are: 128 (default, mode 0) 100 (mode 1)
LCD_NUM_SEG0	Defines the number of available segment outputs of the display controller. Possible values for Sitronix ST7528 are: 132 (default, mode 0) 160 (mode 1)