Supported hardware
Controllers
This driver has been tested with the following LCD controllers
Bits per pixel
Supported color depth is 5 bpp (default) and 4 bpp.
Interfaces
The driver supports 8-bit parallel (simple bus) interface,
3 line SPI or 4 line SPI.
Display data RAM organization
The picture above shows the relation between the display
memory and the SEG and COM lines of the display.
Additional RAM requirements of the driver
This LCD driver may be used with or without a display
data cache, containing a com- plete copy of the contents of the LCD data
RAM. If a cache is not used, there are no additional RAM requirements.
It is optional (but recommended) to use this driver with a data cache
for faster LCD- access. The amount of memory used by the cache may be
calculated as follows:
5bpp mode: Size of RAM (in bytes) = (LCD_XSIZE + 2) / 3 * 3 * LCD_YSIZE
4bpp mode: Size of RAM (in bytes) = ((LCD_XSIZE + 2) / 3 * 3 + 1) / 2 * LCD_YSIZE
Additional driver functions
None.
Hardware configuration
This driver accesses the hardware with a simple bus
interface. The following table lists the macros which must be defined
for hardware access:
| LCD_INIT_CONTROLLER |
Initialization sequence for the LCD controller. |
| LCD_WRITE_A0 |
Write a byte to LCD controller with A-line low. |
| LCD_WRITE_A1 |
Write a byte to LCD controller with A-line high. |
| LCD_WRITEM_A1 |
Write multiple bytes to display controller with A-line high. |
| LCD_READM_A1 |
Read multiple bytes from display controller with A-line high. Required
only if no display data cache is configured. |
Additional configuration switches
None.
Special requirements
None.

Copyright SEGGER Microcontroller GmbH & Co.KG. All
rights reserved.
For more information, please visit our web site
www.segger.com or contact us at info@segger.com
Last update:
December 7, 2007
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