Universal Driver
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Universal NAND flash driver
This driver for NAND flashes is designed to support SLC and MLC NAND flashes. It can correct multiple bit errors by using the internal ECC of NAND flashes or by calling ECC computation routines provided by the application. The ECC protects the sector data and the driver management data stored in the spare area of a page. Sector size is equal to page size and must be at least 2048 bytes. Smaller sector sizes are possible using an additional file system layer. The driver requires very little RAM and is extremely efficient.
Performance and resource usage
The emFile NAND driver has been carefully designed to make effective use of RAM. The amount of RAM required by the driver depends on the runtime configuration and the connected device. In a typical embedded system which uses a 2 GBit NAND flash, the driver requires less than 8 KBytes of RAM.
The NAND Flash has a high read and write performance. For example, on an ARM7 running at 48 MHz, the driver reaches a transfer speed of 1.7 MBytes/sec for writing and 5.5 MBytes/sec for reading.
Supported hardware
Tested and compatible NAND flashes
In general, the driver supports almost all Single-Level Cell NAND flashes (SLC) and Multi-Level Cell NAND flashes (MLC) with a page size greater than 2048+64 bytes.
The table below shows the NAND flashes that have been tested or are compatible with a tested device:
| Manufacturer | Device | Page size [Bytes] | Size [Bits] | Internal ECC |
|---|---|---|---|---|
| Hynix | HY27UF082G2M HY27UF084G2M HY27UG084G2M HY27UG084GDM | 2048+64 2048+64 2048+64 2048+64 | 256Mx8 512Mx8 512Mx8 512Mx8 | no |
| Micron | MT29F2G08AAB | 2048+64 2048+64 2048+64 2048+64 2048+64 2048+64 | 256Mx8 256Mx8 512Mx8 512Mx8 128Mx16 2Gx8 | no |
| Samsung | K9F1G08x0A K9F2G08U0M K9K2G08R0A K9K2G08U0M K9F4G08U0M K9F8G08U0M | 2048+64 2048+64 2048+64 2048+64 2048+64 2048+64 | 256Mx8 256Mx8 256Mx8 256Mx8 512Mx8 1024Mx8 | no |
| ST-Microelectronics | NAND01GR3B NAND01GW3B NAND02GR3B NAND02GW3B NAND04GW3 | 2048+64 2048+64 2048+64 2048+64 2048+64 | 128Mx8 128Mx8 256Mx8 256Mx8 512Mx8 | no |
Support for devices not in this list
Most other NAND flash devices are compatible with one of the supported devices. Thus the driver can be used with these devices or may only need a little modification, which can be easily done. Get in touch with us, if you have questions about support for devices not in this list.
Theory of operation
NAND flash devices are divided into physical blocks and physical pages. One physical block is the smallest erasable unit; one physical page is the smallest writable unit. Large block NAND Flash devices contain blocks made up of 64 pages, each page containing 2112 bytes (2048 data bytes + 64 spare bytes). The first page of a block is reserved for management data.
The driver uses the spare bytes for the following purposes:
- To check if the block is valid.
If they are valid the driver uses this sector. When the driver detects a bad sector, the whole block is marked as invalid and its content is copied to a non-defective block. - To store/load management information
This includes the mapping of pages to logical sectors, the number of times a block has been erased and whether a page contains valid data or not. - To store/load an ECC (Error Correction Code) for data reliability.
When reading a sector, the driver also reads the ECC stored in the spare area of the sector, calculates the ECC based on the read data and compares the ECCs. If the ECCs are not identical, the driver tries to recover the data, based on the read ECC. When writing to a page the ECC is calculated based on the data the driver has to write to the page. The calculated ECC is then stored in the spare area.
Software structure
The NAND Flash driver is split up into different layers, which are shown in the illustration below.
It is possible to use the NAND driver with custom hardware. If port pins or simple memory controller are used to access the flash memory, only the hardware layer needs to be ported, normally no changes to the physical layer are required. If the NAND driver should be used with special memory controller (e.g. special FPGA implementations), the physical layer needs to be adapted. In this case, the hardware layer is not required, because the memory controller manages the hardware access.
Fail-safe operation
The emFile NAND driver is fail-safe. That means that the driver makes only atomic actions and takes the responsibility that the data managed by the file system is always valid. In case of a power loss or a power reset during a write operation, it is always assured that only valid data is stored in the flash. If the power loss interrupts the write operation, the old data will be kept and the block not corrupted.
Wear leveling
Wear leveling is supported by the driver. The procedure ensures that the number of erase cycles remains approximately for all the blocks. The maximum allowed erase count difference is runtime configurable and is by default 5000.
Partial writes
The driver writes only once in any page of the NAND flash between two block erase cycles. The number of partial writes is 1 making the driver conform with any SLC/MLC device.
