emFile supports the use of NAND flashes. An optional driver for NAND flashes is available. The NAND driver requires very little RAM, it can work with sector sizes of 512 bytes or 2 Kbytes (small sectors even on large page NAND flashes) and is extremly efficient. The driver is designed to support one or multiple SLC (Single Level Cell) NAND flashes. The NAND flash driver can also be used to access ATMEL's DataFlash chips. To use it in your system, you will have to provide basic I/O functions for accessing your flash device.

NAND flash organization

A NAND flash is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for command inputs. The erase and program operations are automatically executed. To store data on the NAND flash device, it has to be low-level formatted.
NAND flashes consist of a number of blocks. Every block contains a number of sectors, typically 64. The sectors can be written to individually, one at a time. When writing to a sector, bits can only be written from 1 to 0. Only whole blocks (all sectors in the block) can be erased. Erasing means bringing all memory bits in all sectors of the block to logical 1.
Small NAND flashes (up to 256 Mbytes) have a page size of 528 bytes, 512 for data + 16 spare bytes for storing relevant information (ECC, etc.) to the page. Large NAND devices (256 Mbytes or more) have a page size of 2112 bytes, 2048 bytes for data + 64 bytes for storing relevant information to the page.

For example, a typical NAND flash with a size of 256 MBytes has 2048 blocks of 64 sectors of 2112 bytes (2048 bytes for data + 64 bytes spare area).

Supported hardware

Tested and compatible NAND flashes

In general, the driver supports almost all Single-Level Cell NAND flashes (SLC). This includes NAND flashes with page sizes of 512+16 and 2048+64 bytes.
List of tested and compatible NAND flashes

Tested and compatible DataFlash chips

The NAND flash driver fully supports the ATMEL /DataFlash Cards series up to 32MBit. Currently the following devices are supported:

Manufacturer	Device
ATMEL	AT45DB011B AT45DB021B AT45DB041B AT45DB081B AT45DB161B AT45DB321C AT45BR3214B AT45DCB002 AT45DCB004

Pin description - NAND flashes

Pin description - NAND flashes

DataFlash chips are commonly used when low pin count and easy data transfer are required. DataFlash devices use the following pins:

• Data transfer width is 8 bit.
• Chip Select (CS) sets the card active at low-level and inactive at high level.
• Clock signal must be generated by the target system. The serial flash chips are always in slave mode.
• Bit order requires most significant bit (MSB) to be sent out first.

To setup all these requirements, the NAND flash driver will call the function FS_DF_HW_X_Init(), therefore the function FS_DF_HW_X_Init() can be used to initialize the SPI bus.

Theory of operation

NAND flash devices are divided into physical blocks and physical pages. One physical block is the smallest erasable unit; one physical page is the smallest writable unit. Small block NAND flashes contain of multiple pages. One block contain typically 16 / 32 / 64 pages per block. Every page has a size of 528 bytes (512 data bytes + 16 spare bytes). Large block NAND Flash devices contain blocks made up of 64 pages, each page containing 2112 bytes (2048 data bytes + 64 spare bytes). The driver uses the spare bytes for the following reasons:

1. To check if the data Status byte and block status are valid. If they are valid the driver uses this sector. When the driver detects a bad sector, the whole block is marked as invalid and its content is copied to a non-defective block.
2. To store/read an ECC (Error Correction Code) for data reliability. When reading a sector, the driver also reads the ECC stored in the spare area of the sector, calculates the ECC based on the read data and compares the ECCs. If the ECCs are not identical, the driver tries to recover the data, based on the read ECC. When writing to a page the ECC is calculated based on the data the driver has to write to the page. The calculated ECC is then stored in the spare area.

Error correction code (ECC)

The emFile NAND driver is highly speed optimized and offers a better error detection and correction than a standard memory controller ECC. The ECC is capable of single bit error correction and 2-bit random detection. When a block for which the ECC is computed has 2 or more bit errors, the data cannot be corrected. Standard memory controllers compute an ECC for the complete blocksize (512 / 2048 bytes). The emFile NAND driver computes the ECC for data chunks of 256 bytes (e.g. a page with 2048 bytes is divided into 8 parts of 256 bytes), so the probability to detect and also correct data errors is much higher. This enhancement is realized with a very good performance. The ECC computation of the emFile NAND driver is highly optimized, so that a performance of 18 Mbytes/second can be achieved with a ARM SAM7 running at 48 MHz.

We suggest the use of the the emFile NAND driver without the usage of a memory controller, because the performance of the driver is very high and the error correction is much better if it is controlled from driver side.

Software structure

The NAND Flash driver is split up into different layers, which are shown in the illustration below.

It is possible to use the NAND driver with custom hardware. If port pins or simple memory controller are used to access the flash memory, only the hardware layer needs to be ported, normally no changes to the physical layer are required. If the NAND driver should be used with special memory controller (e.g. special FPGA implementations), the physical layer needs to be adapted. In this case, the hardware layer is not required, because the memory controller manages the hardware access.

Fail-safe operation

The emFile NAND driver is fail-safe. That means that the driver makes only atomic actions and takes the responsibility that the data managed by the file system is always valid. In case of a power loss or a power reset during a write operation, it is always assured that only valid data is stored in the flash. If the power loss interrupts the write operation, the old data will be kept and the block not corrupted.

Wear Leveling

Wear leveling is supported by the driver. Wear leveling makes sure that the number of erase cycles remains approximately equal for each sector. Maximum erase count difference is set to 5. This value specifies a maximum difference of erase counts for different physical sectors before the wear leveling uses the sector with the lowest erase count.