embOS for TLCS900 was developed for and with TOSHIBA's CC900 compiler and supports all memory models offered by this compiler.
The distribution contains an easy to use start workspace for TOSHIBA's Integrated Development Environment.

Resources and performance data

Memory usage
Kernel size (ROM)	approx. 1600 bytes
Kernel RAM usage	41 bytes
RAM usage per task control block	28 bytes
RAM usage per resource semaphore	6 bytes
RAM usage per counting semaphore	2 bytes
RAM usage per mailbox	14 bytes
RAM usage per software timer	14 bytes
RAM usage event	0 bytes
Min. stack-size per task (RAM)	100 bytes
Timing
Context switch time	296 clock cycles (14.8 µs), independent of number of tasks
Interrupt latency time for high priority interrupt	max. 20 clock cycles (1.0 µs)
Kernel CPU usage/TICK	less than .2% of total calculation time at 1000 Interrupts/second (1ms TICK)
Basic time unit (TICK)	typ. 1 ms, min. 10 µs (100 kHz interrupt frequency)
Features
Max. no. of tasks	Unlimited (by available RAM only)
Max. no. of mailboxes	unlimited (by available RAM only)
Max. no. of semaphores (resource/binary/counting)	unlimited (by available RAM only)
Max. no. of software timers	unlimited (by available RAM only)
Max. no. of priorities	255
Stack size idle task (RAM)	0(no memory needed)
Nested interrupts	permitted
Task switches from within ISR	possible

Absolute data given above were measured with embOS release build on a TMP94F53 CPU running at 20MHz in __cdecl memory model.

embOSView offers system analysis during runtime

Available Emulators

• TOSHIBA

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Release notes

Updated:
2003-01-09 [AW] V3.10k
2002-11-24 [AW] V3.10j

1. Tool chain used for build
2. Performance
3. New features
4. Improvements
5. Program corrections
6. Known problems/limitations
7. Release history
8. Miscellaneous

Tool chain used for build

The following tools have been used:

Compiler        :  CC900 V4.51c
Assembler       :  ASM900 V2.2gc
Librarian       :  TULIB V1.2ka
Workbench       :  TIDE V1.0.0.39

Performance

1. Task switch time (default memory model, Release build): 14.8 us = 296 CPU clock cycles


2. Interrupt latency (default memory model, Release build): 1.0 us = 20 CPU clock cycles

Absolute timings are based on 20MHz CPU clock

New features

Version 3.10k

1. OS_GetMailTimed()
   New mailbox retreiving function with timeout.

Version 3.10

1. OS_WaitSingleEvent()
   Unmasked events remain unchanged when function returns.
2. OS_WaitSingleEventTimed()
   Unmasked events remain unchanged when function returns. Timeout for waiting can be specified.

Version 3.09

NONE

Improvements

NONE

Program corrections

Version 3.10k

NONE

Known problems / limitations

NONE

Release history

Version	Release date	Short explanation
V3.10k	09. Jan 2003	OS_GetMailTimed() added, manuals finalized
V3.10j	24. Nov 2002	First release for TLCS 900 CPUs

Miscellaneous

This document was first released with version 3.09 of the software.