embOS for TLCS900 CPUs and TOSHIBA compiler

embOS for TLCS900 was developed for and with TOSHIBA's CC900 compiler and supports all memory models offered by this compiler.
The distribution contains an easy to use start workspace for TOSHIBA's Integrated Development Environment.

Resources and performance data

Memory usage
Kernel size (ROM)	approx. 1600 bytes
Kernel RAM usage	41 bytes
RAM usage per task control block	28 bytes
RAM usage per resource semaphore	6 bytes
RAM usage per counting semaphore	2 bytes
RAM usage per mailbox	14 bytes
RAM usage per software timer	14 bytes
RAM usage event	0 bytes
Min. stack-size per task (RAM)	100 bytes
Timing
Context switch time	296 clock cycles (14.8 µs), independent of number of tasks
Interrupt latency time for high priority interrupt	max. 20 clock cycles (1.0 µs)
Kernel CPU usage/TICK	less than .2% of total calculation time at 1000 Interrupts/second (1ms TICK)
Basic time unit (TICK)	typ. 1 ms, min. 10 µs (100 kHz interrupt frequency)
Features
Max. no. of tasks	Unlimited (by available RAM only)
Max. no. of mailboxes	unlimited (by available RAM only)
Max. no. of semaphores (resource/binary/counting)	unlimited (by available RAM only)
Max. no. of software timers	unlimited (by available RAM only)
Max. no. of priorities	255
Stack size idle task (RAM)	0(no memory needed)
Nested interrupts	permitted
Task switches from within ISR	possible

Absolute data given above were measured with embOS release build on a TMP94F53 CPU running at 20MHz in __cdecl memory model.

embOSView offers system analysis during runtime

embOSView with TOSHIBA TMP94F53 CPU

Available Emulators

TOSHIBA

Additional information

Release Notes embOS T900 for TOSHIBA CC900 compiler