embOS for Renesas R8C CPUs and IAR compiler for R8C

embOS for Renesas R8C was developed for and with IAR's compiler V3.21A for R8C and supports all memory models offered by this compiler. It comes with an easy to use start project for IAR's embedded workbench. Software development with E8 Emulator and CSpy simulator is supported.

Resources and performance data

Memory usage
Kernel size (ROM)	1281 bytes
Kernel RAM usage	28 bytes
RAM usage per task control block	18 bytes
RAM usage per resource semaphore	4 bytes
RAM usage per counting semaphore	2 bytes
RAM usage per mailbox	12 bytes
RAM usage per software timer	12 bytes
RAM usage event	0 bytes
Min. stack-size per task (RAM)	42 bytes
Timing
Context switching time	437 clock cycles (21.85 µs), independent of number of tasks
Interrupt latency time	TBD
Kernel CPU usage/TICK	less than .4% of total calculation time at 1000 Interrupts/second (1ms TICK)
Basic time unit (TICK)	typ. 1 ms, min. 20 µs (50 kHz interrupt frequency)
Features
Max. no. of tasks	Unlimited (by available RAM only)
Max. no. of mailboxes	unlimited (by available RAM only)
Max. no. of semaphores (resource/binary/counting)	unlimited (by available RAM only)
Max. no. of software timers	unlimited (by available RAM only)
Max. no. of priorities	255
Stack size idle task (RAM)	0(no memory needed)
Nested interrupts	permitted
Task switches from within ISR	possible

Absolute timings given above were measured with embOS release build on an R8C/1B CPU running at 20MHz in NEAR memory model.

embOSView offers system analysis during runtime

embOSView with Renesas M16C/62 CPU

Available Emulators

Renesas

Additional information

Release Notes embOS R8C for IAR compiler
IAR Web site for additional compiler info / support
Renesas Web site for additional CPU info / support

Copyright 2001-2007 SEGGER Microcontroller GmbH & Co.KG. All rights reserved.
For more information, please visit our web site www.segger.com or contact us at info@segger.com
Last update: December 7, 2007