embOS for RENESAS H8 / H8S series and IAR compiler

embOS for RENESAS H8/H8S series was developed for and with IAR's compiler and supports H8/H8S CPUs with all memory models offered by this compiler.
It comes with easy to use start projects for IAR's embedded workbench. Software development with CSpy simulator debugger is supported.

Resources and performance data

Memory usage
Kernel size (ROM)	1582 bytes
Kernel RAM usage	34 bytes
RAM usage per task control block	28 bytes
RAM usage per resource semaphore	6 bytes
RAM usage per counting semaphore	2 bytes
RAM usage per mailbox	14 bytes
RAM usage per software timer	14 bytes
RAM usage event	0 bytes
Min. stack-size per task (RAM)	42 bytes
Timing
Context switch time	658 clock cycles (29.9 µs), independent of number of tasks
Interrupt latency time (Fast interrupt)	max. 74 clock cycles (3.3 µs)
Kernel CPU usage/TICK	less than .4% of total calculation time at 1000 Interrupts/second (1ms TICK)
Basic time unit (TICK)	typ. 1 ms, min. 20 µs (50 kHz interrupt frequency)
Features
Max. no. of tasks	Unlimited (by available RAM only)
Max. no. of mailboxes	unlimited (by available RAM only)
Max. no. of semaphores (resource/binary/counting)	unlimited (by available RAM only)
Max. no. of software timers	unlimited (by available RAM only)
Max. no. of priorities	255
Stack size idle task (RAM)	0(no memory needed)
Nested interrupts	permitted
Task switches from within ISR	possible

Absolute timings given above were measured with embOS release build on an H83069 CPU running at 22 MHz in LARGE memory model.

embOSView offers system analysis during runtime

embOSView with RENESAS H8 CPU

Available Emulators

HITACHI
RENESAS

Additional information

Release Notes embOS H8 for IAR compiler
IAR Web site for additional compiler info / support
Renesas Web site for additional CPU info / support