embOS for National Semiconductor CR16C CPUs and IAR compiler

embOS for National Semiconductor CR16C was developed for and with IAR's compiler and supports nearly all memory models offered by this compiler. It comes with an easy to use start project for IAR's embedded workbench. Software development with WinIdea debugger is supported.

Resources and performance data

Memory usage
Kernel size (ROM)	< 1800 bytes
Kernel RAM usage	40 bytes
RAM usage per task control block	28 bytes
RAM usage per resource semaphore	14 bytes
RAM usage per counting semaphore	6 bytes
RAM usage per mailbox	16 bytes
RAM usage per software timer	14 bytes
RAM usage event	0 bytes
Min. stack-size per task (RAM)	28 bytes
Timing
Context switch time	tbd
Interrupt latency time	tbd
Kernel CPU usage/TICK	less than .4% of total calculation time at 1000 Interrupts/second (1ms TICK)
Basic time unit (TICK)	typ. 1 ms, min. 20 µs (50 kHz interrupt frequency)
Features
Max. no. of tasks	Unlimited (by available RAM only)
Max. no. of mailboxes	unlimited (by available RAM only)
Max. no. of semaphores (resource/binary/counting)	unlimited (by available RAM only)
Max. no. of software timers	unlimited (by available RAM only)
Max. no. of priorities	255
Stack size idle task (RAM)	0 (no memory needed)
Nested interrupts	permitted
Task switches from within ISR	possible

Absolute timings given above were measured with embOS release build

embOSView offers system analysis during runtime

embOSView with National CR16C CPU

Additional information

Release Notes embOS CR16C for IAR compiler
IAR Web site for additional compiler info / support

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For more information, please visit our web site www.segger.com or contact us at info@segger.com
Last update: December 7, 2007