Melps M7700, IAR
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Melps M7700, IAR
embOS for Renesas M7700 was developed for and with IAR's compiler and supports all memory models offered by this compiler. It comes with an easy to use start project for IAR's embedded workbench.
Resources and performance data
| Memory usage | |
|---|---|
| Kernel size (ROM) | approx. 970 bytes |
| Kernel RAM usage | 16 bytes |
| RAM usage per task control block | 8 bytes |
| RAM usage per resource semaphore | 8 bytes |
| RAM usage per counting semaphore | 8 bytes |
| RAM usage per mailbox | 7 bytes |
| RAM usage per software timer | 7 bytes |
| RAM usage event | 0 bytes |
| Min. stack-size per task (RAM) | 40 bytes |
| Timing | |
| Context switch time | tbd |
| Interrupt latency time | tbd |
| Kernel CPU usage/TICK | tbd |
| Basic time unit (TICK) | typ. 1 ms, min. 33.3 µs (33.3 kHz interrupt frequency) |
| Features | |
| Max. no. of tasks | Unlimited (by available RAM only) |
| Max. no. of mailboxes | unlimited (by available RAM only) |
| Max. no. of semaphores (resource/binary/counting) | unlimited (by available RAM only) |
| Max. no. of software timers | unlimited (by available RAM only) |
| Max. no. of priorities | 256 |
| Stack size idle task (RAM) | 0(no memory needed) |
| Nested interrupts | permitted |
| Task switches from within ISR | possible |
Values given above were calculated for embOS M7700 with small memory model.
embOSView currently not available for M7700
Available Emulators
- Lauterbach
- Renesas
- HP
Additional information
IAR Web site for additional compiler info / support
Renesas Web site for additional CPU info / support
